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<style><!--
/* Font Definitions */
@font-face
{font-family:Helvetica;
panose-1:2 11 6 4 2 2 2 2 2 4;}
@font-face
{font-family:"Cambria Math";
panose-1:2 4 5 3 5 4 6 3 2 4;}
@font-face
{font-family:Calibri;
panose-1:2 15 5 2 2 2 4 3 2 4;}
@font-face
{font-family:Tahoma;
panose-1:2 11 6 4 3 5 4 4 2 4;}
/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{margin:0cm;
margin-bottom:.0001pt;
font-size:12.0pt;
font-family:"Times New Roman","serif";}
a:link, span.MsoHyperlink
{mso-style-priority:99;
color:blue;
text-decoration:underline;}
a:visited, span.MsoHyperlinkFollowed
{mso-style-priority:99;
color:purple;
text-decoration:underline;}
p
{mso-style-priority:99;
mso-margin-top-alt:auto;
margin-right:0cm;
mso-margin-bottom-alt:auto;
margin-left:0cm;
font-size:12.0pt;
font-family:"Times New Roman","serif";}
p.MsoAcetate, li.MsoAcetate, div.MsoAcetate
{mso-style-priority:99;
mso-style-link:"Balloon Text Char";
margin:0cm;
margin-bottom:.0001pt;
font-size:8.0pt;
font-family:"Tahoma","sans-serif";}
span.EmailStyle18
{mso-style-type:personal-reply;
font-family:"Calibri","sans-serif";
color:#1F497D;}
span.BalloonTextChar
{mso-style-name:"Balloon Text Char";
mso-style-priority:99;
mso-style-link:"Balloon Text";
font-family:"Tahoma","sans-serif";
mso-fareast-language:EN-IE;}
.MsoChpDefault
{mso-style-type:export-only;
font-family:"Calibri","sans-serif";
mso-fareast-language:EN-US;}
@page WordSection1
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margin:72.0pt 72.0pt 72.0pt 72.0pt;}
div.WordSection1
{page:WordSection1;}
--></style><!--[if gte mso 9]><xml>
<o:shapedefaults v:ext="edit" spidmax="1026" />
</xml><![endif]--><!--[if gte mso 9]><xml>
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<o:idmap v:ext="edit" data="1" />
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">></span> PCI ids will be different<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Oh - what do you mean by the Sean?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I am still trying to understand why for two identical CPUID/Stepping E3815s, with the same 8BM flash image, I get different PCI device ids for the Soc Transaction Router ( 0000 rather than 0f00 ) and Video ( 0031 rather than 0f00 ). Is
this related?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I’ve asked Intel Premier Support but heard nothing back yet. Still puzzled :o)<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Mike.<span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> coreboot [mailto:coreboot-bounces@coreboot.org]
<b>On Behalf Of </b>Sean McNeil<br>
<b>Sent:</b> 20 June 2014 11:26<br>
<b>To:</b> Gerald Otter<br>
<b>Cc:</b> Wen Wang; coreboot<br>
<b>Subject:</b> Re: [coreboot] latest baytrail fsp on CRB<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p>PCI ids will be different. Plus some devices may be disabled.<o:p></o:p></p>
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<p class="MsoNormal">On Jun 20, 2014 5:21 PM, "Gerald Otter" <<a href="mailto:gerald.otter@gmail.com">gerald.otter@gmail.com</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal">As Mike mentioned earlier, you need the TXE ( located in top 6MB ) from BYT-I_SEC_DUAL_BOOT_PV_GOLD.<o:p></o:p></p>
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<p class="MsoNormal">The TXE from the BIOS’s you mentioned don’t work with coreboot. I ran into the same issue as you.<o:p></o:p></p>
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<p class="MsoNormal">Alternatively you can erase the top 6MB to start in non-descriptor mode. I don’t think this matters much for coreboot’s startup process, but could be wrong. <o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Gerald<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On 19 Jun 2014, at 23:08, Wen Wang <<a href="mailto:wen.wang@adiengineering.com" target="_blank">wen.wang@adiengineering.com</a>> wrote:<o:p></o:p></p>
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<br>
<o:p></o:p></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">I went back to the commit (Martin’s commit d75800c7f2476bee243cc22255acb54d6676d4bc back in late May) that seems work for a few people on the list. I also thought
it was working better for me too as I was observing coreboot and fsp booting until it failed at SeaBIOS. It turned out I had a pilot error flashing the image. I thought I flashed the top 2M of the flash, but my script accidentally erased the bottom 6M. Surprisingly
it booted quite far. Anyhow, after I corrected my script today (flashing only the top 2M, leaving rest from BIOS). Nothing happens, port 80 remains 0, no console output. Here is cbfstool print, my config file is attached to an earlier post,<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""> <o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">[wenwang@localhost coreboot]$ build/cbfstool build/coreboot.rom print<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">coreboot.rom: 2048 kB, bootblocksize 1024, romsize 2097152, offset 0x0<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">alignment: 64 bytes<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""> <o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Name Offset Type Size<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">cmos_layout.bin 0x0 cmos_layout 1132<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">pci8086,0f31.rom 0x4c0 optionrom 65536<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">fallback/romstage 0x10500 stage 27029<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">fallback/ramstage 0x16f00 stage 58966<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">fallback/payload 0x255c0 payload 59949<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">config 0x34040 raw 4239<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">(empty) 0x35100 null 896728<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">cpu_microcode_blob.bin 0x110000 microcode 52224<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">(empty) 0x11cc40 null 209752<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">mrc.cache 0x14ffc0 (unknown) 65536<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">(empty) 0x160000 null 393112<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">fsp.bin 0x1bffc0 (unknown) 229376<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">(empty) 0x1f8000 null 31640<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""> <o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Could it be my BIOS issue? I tried both 64 and 32-bit BIOS from 540469_540469_BYT_l_66_41_ReleasePackage and 543844_543844_BYTI_080_011_ReleasePackage. None
of them works with my coreboot build. . Can somebody please share the working BIOS version?<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""> <o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Thanks,<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""> <o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Wen<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p></o:p></span></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">From:</span></b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""> Mike Hibbett [<a href="mailto:mhibbett@ircona.com" target="_blank">mailto:mhibbett@ircona.com</a>] <br>
<b>Sent:</b> Wednesday, June 18, 2014 4:58 PM<br>
<b>To:</b> Wen Wang; Mike Hibbett; <a href="mailto:coreboot@coreboot.org" target="_blank">
coreboot@coreboot.org</a><br>
<b>Subject:</b> Re: [coreboot] latest baytrail fsp on CRB<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""> <o:p></o:p></span></p>
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<p><span lang="EN-US">Use the one that came with your board, or get the latest From the IBL. I forget the document number but the file is called byt-i_sec_dual_boot_pv_gold<o:p></o:p></span></p>
<p><span lang="EN-US">Mike<o:p></o:p></span></p>
<p><span lang="EN-US">Sent with AquaMail for Android<br>
<a href="http://www.aqua-mail.com/" target="_blank"><span style="color:#954F72">http://www.aqua-mail.com</span></a><o:p></o:p></span></p>
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<p style="margin-bottom:10.0pt"><span lang="EN-US">On 18 June 2014 21:15:51 Wen Wang <<a href="mailto:wen.wang@adiengineering.com" target="_blank"><span style="color:#954F72">wen.wang@adiengineering.com</span></a>> wrote:<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">.config file attached.</span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Also what should I do for flash descriptor?</span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Thanks,</span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Wen</span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p></o:p></span></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">From:</span></b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""> Mike Hibbett [<a href="mailto:mhibbett@ircona.com" target="_blank"><span style="color:#954F72">mailto:mhibbett@ircona.com</span></a>] <br>
<b>Sent:</b> Wednesday, June 18, 2014 2:29 PM<br>
<b>To:</b> Wen Wang; <a href="mailto:coreboot@coreboot.org" target="_blank"><span style="color:#954F72">coreboot@coreboot.org</span></a><br>
<b>Subject:</b> Re: [coreboot] latest baytrail fsp on CRB<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""> <o:p></o:p></span></p>
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<p><span lang="EN-US" style="font-family:"Arial","sans-serif"">Can you post your coreboot .config file?</span><span lang="EN-US"><o:p></o:p></span></p>
<p><span lang="EN-US" style="font-family:"Arial","sans-serif"">I'm booting bayley bay with a b3 e3815.</span><span lang="EN-US"><o:p></o:p></span></p>
<p><span lang="EN-US" style="font-family:"Arial","sans-serif"">Mike</span><span lang="EN-US"><o:p></o:p></span></p>
<p><span lang="EN-US" style="font-family:"Arial","sans-serif"">Sent with AquaMail for Android<br>
<a href="http://www.aqua-mail.com/" target="_blank"><span style="color:#954F72">http://www.aqua-mail.com</span></a></span><span lang="EN-US"><o:p></o:p></span></p>
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<p style="margin-bottom:10.0pt"><span lang="EN-US" style="font-family:"Arial","sans-serif"">On 18 June 2014 19:13:49 Wen Wang <<a href="mailto:wen.wang@adiengineering.com" target="_blank"><span style="color:#954F72">wen.wang@adiengineering.com</span></a>> wrote:</span><span lang="EN-US"><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Hi all,<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""> <o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Has anybody been able to boot Bayley Bay CRB with the latest coreboot source from the git tree? We have a Bayley Bay CRB (E3827, B3). With coreboot Baytrail
fsp support pulled from about two weeks ago and some help from Martin, I was able to see coreboot booting and fsp loaded, but was having issues with SeaBIOS. I pulled latest source tree this morning and found out it does not boot any more on my board. Port
80 stuck at code 0x43, no console output.<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""> <o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Here are my steps:<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">1.</span><span lang="EN-US" style="font-size:7.0pt"> </span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Build coreboot
toolchain.<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">2.</span><span lang="EN-US" style="font-size:7.0pt"> </span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Build coreboot.rom
using fsp and microcode from BAY_TRAIL_FSP_KIT downloaded from Intel fsp site.<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">3.</span><span lang="EN-US" style="font-size:7.0pt"> </span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Flash coreboot.rom
to top 2M of the 8M flash.<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""> <o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">I was getting the usage information here and there from the discussion threads and perhaps I missed something? It would be great if somebody could post the detailed
procedure.<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""> <o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Thanks!<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif""> <o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">-- <br>
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--<br>
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