<p dir="ltr">PCI ids will be different. Plus some devices may be disabled.</p>
<div class="gmail_quote">On Jun 20, 2014 5:21 PM, "Gerald Otter" <<a href="mailto:gerald.otter@gmail.com">gerald.otter@gmail.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div style="word-wrap:break-word">As Mike mentioned earlier, you need the TXE ( located in top 6MB ) from BYT-I_SEC_DUAL_BOOT_PV_GOLD.<div>The TXE from the BIOS’s you mentioned don’t work with coreboot. I ran into the same issue as you.</div>
<div>Alternatively you can erase the top 6MB to start in non-descriptor mode. I don’t think this matters much for coreboot’s startup process, but could be wrong. </div><div><br></div><div>Gerald</div><div><br><div><div><div>
On 19 Jun 2014, at 23:08, Wen Wang <<a href="mailto:wen.wang@adiengineering.com" target="_blank">wen.wang@adiengineering.com</a>> wrote:</div><br><blockquote type="cite"><div lang="EN-US" link="#0563C1" vlink="#954F72" style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px">
<div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">I went back to the commit (Martin’s commit d75800c7f2476bee243cc22255acb54d6676d4bc back in late May) that seems work for a few people on the list. I also thought it was working better for me too as I was observing coreboot and fsp booting until it failed at SeaBIOS. It turned out I had a pilot error flashing the image. I thought I flashed the top 2M of the flash, but my script accidentally erased the bottom 6M. Surprisingly it booted quite far. Anyhow, after I corrected my script today (flashing only the top 2M, leaving rest from BIOS). Nothing happens, port 80 remains 0, no console output. Here is cbfstool print, my config file is attached to an earlier post,<u></u><u></u></div>
<div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"><u></u> <u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">[wenwang@localhost coreboot]$ build/cbfstool build/coreboot.rom print<u></u><u></u></div>
<div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">coreboot.rom: 2048 kB, bootblocksize 1024, romsize 2097152, offset 0x0<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">
alignment: 64 bytes<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"><u></u> <u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">
Name Offset Type Size<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">cmos_layout.bin 0x0 cmos_layout 1132<u></u><u></u></div>
<div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">pci8086,0f31.rom 0x4c0 optionrom 65536<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">
fallback/romstage 0x10500 stage 27029<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">fallback/ramstage 0x16f00 stage 58966<u></u><u></u></div>
<div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">fallback/payload 0x255c0 payload 59949<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">
config 0x34040 raw 4239<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">(empty) 0x35100 null 896728<u></u><u></u></div>
<div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">cpu_microcode_blob.bin 0x110000 microcode 52224<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">
(empty) 0x11cc40 null 209752<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">mrc.cache 0x14ffc0 (unknown) 65536<u></u><u></u></div>
<div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">(empty) 0x160000 null 393112<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">
fsp.bin 0x1bffc0 (unknown) 229376<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">(empty) 0x1f8000 null 31640<u></u><u></u></div>
<div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"><u></u> <u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">Could it be my BIOS issue? I tried both 64 and 32-bit BIOS from 540469_540469_BYT_l_66_41_ReleasePackage and 543844_543844_BYTI_080_011_ReleasePackage. None of them works with my coreboot build. . Can somebody please share the working BIOS version?<u></u><u></u></div>
<div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"><u></u> <u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">Thanks,<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">
<u></u> <u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">Wen<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"><span style="color:rgb(31,73,125)"> </span></div>
<div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"><span style="color:rgb(31,73,125)"> </span></div><div><div style="border-style:solid none none;border-top-color:rgb(225,225,225);border-top-width:1pt;padding:3pt 0in 0in">
<div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"><b>From:</b><span> </span>Mike Hibbett [<a href="mailto:mhibbett@ircona.com" target="_blank">mailto:mhibbett@ircona.com</a>]<span> </span><br>
<b>Sent:</b><span> </span>Wednesday, June 18, 2014 4:58 PM<br><b>To:</b><span> </span>Wen Wang; Mike Hibbett; <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br><b>Subject:</b><span> </span>Re: [coreboot] latest baytrail fsp on CRB<u></u><u></u></div>
</div></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"><u></u> <u></u></div><div><p style="margin-right:0in;margin-left:0in;font-size:12pt;font-family:'Times New Roman',serif">
Use the one that came with your board, or get the latest From the IBL. I forget the document number but the file is called byt-i_sec_dual_boot_pv_gold<u></u><u></u></p><p style="margin-right:0in;margin-left:0in;font-size:12pt;font-family:'Times New Roman',serif">
Mike<u></u><u></u></p><p style="margin-right:0in;margin-left:0in;font-size:12pt;font-family:'Times New Roman',serif">Sent with AquaMail for Android<br><a href="http://www.aqua-mail.com/" style="color:rgb(149,79,114);text-decoration:underline" target="_blank">http://www.aqua-mail.com</a><u></u><u></u></p>
<div><p style="margin-right:0in;margin-left:0in;font-size:12pt;font-family:'Times New Roman',serif;margin-bottom:10pt"><span>On 18 June 2014 21:15:51 Wen Wang <<a href="mailto:wen.wang@adiengineering.com" style="color:rgb(149,79,114);text-decoration:underline" target="_blank">wen.wang@adiengineering.com</a>> wrote:<u></u><u></u></span></p>
<blockquote style="border-style:none none none solid;border-left-color:gray;border-left-width:1pt;padding:0in 0in 0in 5pt;margin-left:4.5pt;margin-right:0in"><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">
<span style="color:rgb(31,73,125)">.config file attached.</span><u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"><span style="color:rgb(31,73,125)"> </span><u></u><u></u></div>
<div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"><span style="color:rgb(31,73,125)">Also what should I do for flash descriptor?</span><u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">
<span style="color:rgb(31,73,125)"> </span><u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"><span style="color:rgb(31,73,125)">Thanks,</span><u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">
<span style="color:rgb(31,73,125)"> </span><u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"><span style="color:rgb(31,73,125)">Wen</span><u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">
<span style="color:rgb(31,73,125)"> </span><u></u><u></u></div><div><div style="border-style:solid none none;border-top-color:rgb(225,225,225);border-top-width:1pt;padding:3pt 0in 0in"><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">
<b>From:</b><span> </span>Mike Hibbett [<a href="mailto:mhibbett@ircona.com" style="color:rgb(149,79,114);text-decoration:underline" target="_blank">mailto:mhibbett@ircona.com</a>]<span> </span><br><b>Sent:</b><span> </span>Wednesday, June 18, 2014 2:29 PM<br>
<b>To:</b><span> </span>Wen Wang;<span> </span><a href="mailto:coreboot@coreboot.org" style="color:rgb(149,79,114);text-decoration:underline" target="_blank">coreboot@coreboot.org</a><br><b>Subject:</b><span> </span>Re: [coreboot] latest baytrail fsp on CRB<u></u><u></u></div>
</div></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"> <u></u><u></u></div><div><p style="margin-right:0in;margin-left:0in;font-size:12pt;font-family:'Times New Roman',serif">
<span style="font-family:Arial,sans-serif">Can you post your coreboot .config file?</span><u></u><u></u></p><p style="margin-right:0in;margin-left:0in;font-size:12pt;font-family:'Times New Roman',serif"><span style="font-family:Arial,sans-serif">I'm booting bayley bay with a b3 e3815.</span><u></u><u></u></p>
<p style="margin-right:0in;margin-left:0in;font-size:12pt;font-family:'Times New Roman',serif"><span style="font-family:Arial,sans-serif">Mike</span><u></u><u></u></p><p style="margin-right:0in;margin-left:0in;font-size:12pt;font-family:'Times New Roman',serif">
<span style="font-family:Arial,sans-serif">Sent with AquaMail for Android<br><a href="http://www.aqua-mail.com/" style="color:rgb(149,79,114);text-decoration:underline" target="_blank">http://www.aqua-mail.com</a></span><u></u><u></u></p>
<div><p style="margin-right:0in;margin-left:0in;font-size:12pt;font-family:'Times New Roman',serif;margin-bottom:10pt"><span style="font-family:Arial,sans-serif">On 18 June 2014 19:13:49 Wen Wang <<a href="mailto:wen.wang@adiengineering.com" style="color:rgb(149,79,114);text-decoration:underline" target="_blank">wen.wang@adiengineering.com</a>> wrote:</span><u></u><u></u></p>
<blockquote style="border-style:none none none solid;border-left-color:gray;border-left-width:1pt;padding:0in 0in 0in 5pt;margin:5pt 0in 5pt 4.5pt"><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">
Hi all,<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"> <u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">Has anybody been able to boot Bayley Bay CRB with the latest coreboot source from the git tree? We have a Bayley Bay CRB (E3827, B3). With coreboot Baytrail fsp support pulled from about two weeks ago and some help from Martin, I was able to see coreboot booting and fsp loaded, but was having issues with SeaBIOS. I pulled latest source tree this morning and found out it does not boot any more on my board. Port 80 stuck at code 0x43, no console output.<u></u><u></u></div>
<div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"> <u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">Here are my steps:<u></u><u></u></div>
<div style="margin:0in 0in 0.0001pt 0.5in;font-size:11pt;font-family:Calibri,sans-serif">1.<span style="font-size:7pt;font-family:'Times New Roman',serif"> <span> </span></span>Build coreboot toolchain.<u></u><u></u></div>
<div style="margin:0in 0in 0.0001pt 0.5in;font-size:11pt;font-family:Calibri,sans-serif">2.<span style="font-size:7pt;font-family:'Times New Roman',serif"> <span> </span></span>Build coreboot.rom using fsp and microcode from BAY_TRAIL_FSP_KIT downloaded from Intel fsp site.<u></u><u></u></div>
<div style="margin:0in 0in 0.0001pt 0.5in;font-size:11pt;font-family:Calibri,sans-serif">3.<span style="font-size:7pt;font-family:'Times New Roman',serif"> <span> </span></span>Flash coreboot.rom to top 2M of the 8M flash.<u></u><u></u></div>
<div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"> <u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">I was getting the usage information here and there from the discussion threads and perhaps I missed something? It would be great if somebody could post the detailed procedure.<u></u><u></u></div>
<div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif"> <u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">Thanks!<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">
<u></u><u></u></div><div style="margin:0in 0in 0.0001pt;font-size:11pt;font-family:Calibri,sans-serif">Wen<u></u><u></u></div></blockquote></div></div></blockquote></div></div></div>--<span> </span><br>coreboot mailing list: <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br>
<a href="http://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">http://www.coreboot.org/mailman/listinfo/coreboot</a></div></blockquote></div><br></div></div></div><br>--<br>
coreboot mailing list: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
<a href="http://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">http://www.coreboot.org/mailman/listinfo/coreboot</a><br></blockquote></div>