<div dir="ltr"><div><div><div>hi,<br><br></div>i did some experiments with the baytrail fsp coreboot and first of all i like to say thanks for all the good code! everything looks much better than the last time i tried to do anything with coreboot.<br>
<br></div>for the problems - maybe there is something wrong with reading the ids. i found that on my platform it seems like fsp is change mmio base address. so pci reads will not work there after and read all ff. <br><br>
<br></div><div>maybe there should be a check which reads back mmio and does some debug log. a example for access to the base address is in <span class="">setup_mmconfig</span><span class=""></span></div><div><br><br></div>
<div>regards,<br></div></div><div class="gmail_extra"><br><br><div class="gmail_quote">2014-06-20 12:33 GMT+02:00 Mike Hibbett <span dir="ltr"><<a href="mailto:mhibbett@ircona.com" target="_blank">mhibbett@ircona.com</a>></span>:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div link="blue" vlink="purple" lang="EN-IE">
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">></span> PCI ids will be different<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">Oh - what do you mean by the Sean?<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">I am still trying to understand why for two identical CPUID/Stepping E3815s, with the same 8BM flash image, I get different PCI device ids for the Soc Transaction Router ( 0000 rather than 0f00 ) and Video ( 0031 rather than 0f00 ). Is
this related?<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">I’ve asked Intel Premier Support but heard nothing back yet. Still puzzled :o)<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">Mike.<span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"" lang="EN-US">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"" lang="EN-US"> coreboot [mailto:<a href="mailto:coreboot-bounces@coreboot.org" target="_blank">coreboot-bounces@coreboot.org</a>]
<b>On Behalf Of </b>Sean McNeil<br>
<b>Sent:</b> 20 June 2014 11:26<br>
<b>To:</b> Gerald Otter<br>
<b>Cc:</b> Wen Wang; coreboot</span></p><div><div class="h5"><br>
<b>Subject:</b> Re: [coreboot] latest baytrail fsp on CRB<u></u><u></u></div></div><p></p><div><div class="h5">
<p class="MsoNormal"><u></u> <u></u></p>
<p>PCI ids will be different. Plus some devices may be disabled.<u></u><u></u></p>
<div>
<p class="MsoNormal">On Jun 20, 2014 5:21 PM, "Gerald Otter" <<a href="mailto:gerald.otter@gmail.com" target="_blank">gerald.otter@gmail.com</a>> wrote:<u></u><u></u></p>
<div>
<p class="MsoNormal">As Mike mentioned earlier, you need the TXE ( located in top 6MB ) from BYT-I_SEC_DUAL_BOOT_PV_GOLD.<u></u><u></u></p>
<div>
<p class="MsoNormal">The TXE from the BIOS’s you mentioned don’t work with coreboot. I ran into the same issue as you.<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal">Alternatively you can erase the top 6MB to start in non-descriptor mode. I don’t think this matters much for coreboot’s startup process, but could be wrong. <u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">Gerald<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
<div>
<div>
<div>
<p class="MsoNormal">On 19 Jun 2014, at 23:08, Wen Wang <<a href="mailto:wen.wang@adiengineering.com" target="_blank">wen.wang@adiengineering.com</a>> wrote:<u></u><u></u></p>
</div>
<p class="MsoNormal"><br>
<br>
<u></u><u></u></p>
<div>
<div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">I went back to the commit (Martin’s commit d75800c7f2476bee243cc22255acb54d6676d4bc back in late May) that seems work for a few people on the list. I also thought
it was working better for me too as I was observing coreboot and fsp booting until it failed at SeaBIOS. It turned out I had a pilot error flashing the image. I thought I flashed the top 2M of the flash, but my script accidentally erased the bottom 6M. Surprisingly
it booted quite far. Anyhow, after I corrected my script today (flashing only the top 2M, leaving rest from BIOS). Nothing happens, port 80 remains 0, no console output. Here is cbfstool print, my config file is attached to an earlier post,<u></u><u></u></span></p>
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<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"> <u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">[wenwang@localhost coreboot]$ build/cbfstool build/coreboot.rom print<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">coreboot.rom: 2048 kB, bootblocksize 1024, romsize 2097152, offset 0x0<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">alignment: 64 bytes<u></u><u></u></span></p>
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<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"> <u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">Name Offset Type Size<u></u><u></u></span></p>
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<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">cmos_layout.bin 0x0 cmos_layout 1132<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">pci8086,0f31.rom 0x4c0 optionrom 65536<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">fallback/romstage 0x10500 stage 27029<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">fallback/ramstage 0x16f00 stage 58966<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">fallback/payload 0x255c0 payload 59949<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">config 0x34040 raw 4239<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">(empty) 0x35100 null 896728<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">cpu_microcode_blob.bin 0x110000 microcode 52224<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">(empty) 0x11cc40 null 209752<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">mrc.cache 0x14ffc0 (unknown) 65536<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">(empty) 0x160000 null 393112<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">fsp.bin 0x1bffc0 (unknown) 229376<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">(empty) 0x1f8000 null 31640<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"> <u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">Could it be my BIOS issue? I tried both 64 and 32-bit BIOS from 540469_540469_BYT_l_66_41_ReleasePackage and 543844_543844_BYTI_080_011_ReleasePackage. None
of them works with my coreboot build. . Can somebody please share the working BIOS version?<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"> <u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">Thanks,<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"> <u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">Wen<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d" lang="EN-US"> </span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"><u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d" lang="EN-US"> </span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"><u></u><u></u></span></p>
</div>
<div>
<div style="border:none;border-top:solid #e1e1e1 1.0pt;padding:3.0pt 0cm 0cm 0cm">
<div>
<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"> Mike Hibbett [<a href="mailto:mhibbett@ircona.com" target="_blank">mailto:mhibbett@ircona.com</a>] <br>
<b>Sent:</b> Wednesday, June 18, 2014 4:58 PM<br>
<b>To:</b> Wen Wang; Mike Hibbett; <a href="mailto:coreboot@coreboot.org" target="_blank">
coreboot@coreboot.org</a><br>
<b>Subject:</b> Re: [coreboot] latest baytrail fsp on CRB<u></u><u></u></span></p>
</div>
</div>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"> <u></u><u></u></span></p>
</div>
<div>
<p><span lang="EN-US">Use the one that came with your board, or get the latest From the IBL. I forget the document number but the file is called byt-i_sec_dual_boot_pv_gold<u></u><u></u></span></p>
<p><span lang="EN-US">Mike<u></u><u></u></span></p>
<p><span lang="EN-US">Sent with AquaMail for Android<br>
<a href="http://www.aqua-mail.com/" target="_blank"><span style="color:#954f72">http://www.aqua-mail.com</span></a><u></u><u></u></span></p>
<div>
<p style="margin-bottom:10.0pt"><span lang="EN-US">On 18 June 2014 21:15:51 Wen Wang <<a href="mailto:wen.wang@adiengineering.com" target="_blank"><span style="color:#954f72">wen.wang@adiengineering.com</span></a>> wrote:<u></u><u></u></span></p>
<blockquote style="border:none;border-left:solid gray 1.0pt;padding:0cm 0cm 0cm 5.0pt;margin-left:4.5pt;margin-top:5.0pt;margin-right:0cm;margin-bottom:5.0pt">
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d" lang="EN-US">.config file attached.</span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"><u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d" lang="EN-US"> </span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"><u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d" lang="EN-US">Also what should I do for flash descriptor?</span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"><u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d" lang="EN-US"> </span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"><u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d" lang="EN-US">Thanks,</span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"><u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d" lang="EN-US"> </span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"><u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d" lang="EN-US">Wen</span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"><u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d" lang="EN-US"> </span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"><u></u><u></u></span></p>
</div>
<div>
<div style="border:none;border-top:solid #e1e1e1 1.0pt;padding:3.0pt 0cm 0cm 0cm">
<div>
<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"> Mike Hibbett [<a href="mailto:mhibbett@ircona.com" target="_blank"><span style="color:#954f72">mailto:mhibbett@ircona.com</span></a>] <br>
<b>Sent:</b> Wednesday, June 18, 2014 2:29 PM<br>
<b>To:</b> Wen Wang; <a href="mailto:coreboot@coreboot.org" target="_blank"><span style="color:#954f72">coreboot@coreboot.org</span></a><br>
<b>Subject:</b> Re: [coreboot] latest baytrail fsp on CRB<u></u><u></u></span></p>
</div>
</div>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"> <u></u><u></u></span></p>
</div>
<div>
<p><span style="font-family:"Arial","sans-serif"" lang="EN-US">Can you post your coreboot .config file?</span><span lang="EN-US"><u></u><u></u></span></p>
<p><span style="font-family:"Arial","sans-serif"" lang="EN-US">I'm booting bayley bay with a b3 e3815.</span><span lang="EN-US"><u></u><u></u></span></p>
<p><span style="font-family:"Arial","sans-serif"" lang="EN-US">Mike</span><span lang="EN-US"><u></u><u></u></span></p>
<p><span style="font-family:"Arial","sans-serif"" lang="EN-US">Sent with AquaMail for Android<br>
<a href="http://www.aqua-mail.com/" target="_blank"><span style="color:#954f72">http://www.aqua-mail.com</span></a></span><span lang="EN-US"><u></u><u></u></span></p>
<div>
<p style="margin-bottom:10.0pt"><span style="font-family:"Arial","sans-serif"" lang="EN-US">On 18 June 2014 19:13:49 Wen Wang <<a href="mailto:wen.wang@adiengineering.com" target="_blank"><span style="color:#954f72">wen.wang@adiengineering.com</span></a>> wrote:</span><span lang="EN-US"><u></u><u></u></span></p>
<blockquote style="border:none;border-left:solid gray 1.0pt;padding:0cm 0cm 0cm 5.0pt;margin-left:4.5pt;margin-top:5.0pt;margin-right:0cm;margin-bottom:5.0pt">
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">Hi all,<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"> <u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">Has anybody been able to boot Bayley Bay CRB with the latest coreboot source from the git tree? We have a Bayley Bay CRB (E3827, B3). With coreboot Baytrail
fsp support pulled from about two weeks ago and some help from Martin, I was able to see coreboot booting and fsp loaded, but was having issues with SeaBIOS. I pulled latest source tree this morning and found out it does not boot any more on my board. Port
80 stuck at code 0x43, no console output.<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"> <u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">Here are my steps:<u></u><u></u></span></p>
</div>
<div style="margin-left:36.0pt">
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">1.</span><span style="font-size:7.0pt" lang="EN-US"> </span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">Build coreboot
toolchain.<u></u><u></u></span></p>
</div>
<div style="margin-left:36.0pt">
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">2.</span><span style="font-size:7.0pt" lang="EN-US"> </span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">Build coreboot.rom
using fsp and microcode from BAY_TRAIL_FSP_KIT downloaded from Intel fsp site.<u></u><u></u></span></p>
</div>
<div style="margin-left:36.0pt">
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">3.</span><span style="font-size:7.0pt" lang="EN-US"> </span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">Flash coreboot.rom
to top 2M of the 8M flash.<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"> <u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">I was getting the usage information here and there from the discussion threads and perhaps I missed something? It would be great if somebody could post the detailed
procedure.<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"> <u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">Thanks!<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US"> <u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"" lang="EN-US">Wen<u></u><u></u></span></p>
</div>
</blockquote>
</div>
</div>
</blockquote>
</div>
</div>
</div>
<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"" lang="EN-US">-- <br>
coreboot mailing list: <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br>
<a href="http://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">http://www.coreboot.org/mailman/listinfo/coreboot</a><u></u><u></u></span></p>
</div>
</div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
</div>
</div>
<p class="MsoNormal"><br>
--<br>
coreboot mailing list: <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br>
<a href="http://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">http://www.coreboot.org/mailman/listinfo/coreboot</a><u></u><u></u></p>
</div>
</div></div></div>
</div>
<br>--<br>
coreboot mailing list: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
<a href="http://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">http://www.coreboot.org/mailman/listinfo/coreboot</a><br></blockquote></div><br></div>