coreboot-unknown Thu Jul 10 16:15:02 EDT 2014 starting...
picked entry 1 from cache block
MRC cache present at fff73000.
FSP NVRAM Hob at 0x2275d8 (size = 0x2280).
Re-Initializing CBMEM area to 0x7fde0000
Initializing CBMEM area to 0x7fde0000 (131072 bytes)
Adding CBMEM entry as no. 1
Relocate MRC DATA from 002275d8 to 7fde0200 (8832 bytes)
Setting up static southbridge registers...
Setting up graphic registers...
Loading image.
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (671744 bytes), entry @ 0x100000
Jumping to image.
coreboot-unknown Thu Jul 10 16:15:02 EDT 2014 booting...
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:17.0: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.3: enabled 1
Compare with tree...
Root Device: enabled 1
 APIC_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 PCI_DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:01.0: enabled 1
  PCI: 00:02.0: enabled 1
  PCI: 00:03.0: enabled 1
  PCI: 00:04.0: enabled 1
  PCI: 00:11.0: enabled 1
  PCI: 00:15.0: enabled 1
  PCI: 00:13.0: enabled 1
  PCI: 00:16.0: enabled 1
  PCI: 00:17.0: enabled 1
  PCI: 00:18.0: enabled 1
  PCI: 00:1f.0: enabled 1
  PCI: 00:1f.3: enabled 1
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0000] ops
PCI: 00:00.0 [8086/1f0b] enabled
PCI: 00:01.0 [8086/0000] bus ops
PCI: 00:01.0 [8086/1f10] enabled
PCI: Static device PCI: 00:02.0 not found, disabling it. id read=0xffffffff
PCI: 00:03.0 [8086/0000] bus ops
PCI: 00:03.0 [8086/1f12] enabled
PCI: Static device PCI: 00:04.0 not found, disabling it. id read=0xffffffff
PCI: 00:0b.0 [8086/1f18] enabled
PCI: 00:0e.0 [8086/1f14] enabled
PCI: 00:0f.0 [8086/1f16] enabled
PCI: Static device PCI: 00:11.0 not found, disabling it. id read=0xffffffff
PCI: 00:13.0 [8086/1f15] enabled
PCI: 00:14.0 [8086/1f41] enabled
PCI: 00:14.1 [8086/1f41] enabled
PCI: 00:14.2 [8086/1f41] enabled
PCI: 00:14.3 [8086/1f41] enabled
PCI: Static device PCI: 00:15.0 not found, disabling it. id read=0xffffffff
PCI: 00:16.0 [8086/0000] ops
PCI: 00:16.0 [8086/1f2c] enabled
PCI: 00:17.0 [8086/0000] ops
PCI: 00:17.0 [8086/1f22] enabled
PCI: 00:18.0 [8086/0000] ops
PCI: 00:18.0 [8086/1f32] enabled
PCI: 00:1f.0 [8086/0000] bus ops
PCI: 00:1f.0 [8086/1f38] enabled
PCI: 00:1f.3 [8086/0000] bus ops
PCI: 00:1f.3 [8086/1f3c] enabled
[ww] do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
[ww] do_pci_scan_bridge for PCI: 00:03.0
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [8086/1539] enabled
PCI: pci_scan_bus returning with max=002
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x11 @ 0x70
Capability: type 0x10 @ 0xa0
Capability: type 0x10 @ 0x40
do_pci_scan_bridge returns max 2
scan_static_bus for PCI: 00:1f.0
scan_static_bus for PCI: 00:1f.0 done
scan_static_bus for PCI: 00:1f.3
scan_static_bus for PCI: 00:1f.3 done
PCI: pci_scan_bus returning with max=002
scan_static_bus for Root Device done
done
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
Adding PCIe enhanced config space BAR 0xe0000000-0xe4000000.
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:03.0 read_resources bus 2 link: 0
PCI: 00:03.0 read_resources bus 2 link: 0 done
rangeley_lpc_read_resources
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:00.0 resource base e0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
   PCI: 00:01.0
   PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
   PCI: 00:02.0
   PCI: 00:03.0 child on link 0 PCI: 02:00.0
   PCI: 00:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:03.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
    PCI: 02:00.0
    PCI: 02:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
    PCI: 02:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
    PCI: 02:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
   PCI: 00:04.0
   PCI: 00:0b.0
   PCI: 00:0b.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 18
   PCI: 00:0b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
   PCI: 00:0e.0
   PCI: 00:0f.0
   PCI: 00:11.0
   PCI: 00:13.0
   PCI: 00:13.0 resource base 0 size 400 align 10 gran 10 limit ffffffffffffffff flags 201 index 10
   PCI: 00:14.0
   PCI: 00:14.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
   PCI: 00:14.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
   PCI: 00:14.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
   PCI: 00:14.1
   PCI: 00:14.1 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
   PCI: 00:14.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
   PCI: 00:14.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
   PCI: 00:14.2
   PCI: 00:14.2 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
   PCI: 00:14.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
   PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
   PCI: 00:14.3
   PCI: 00:14.3 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
   PCI: 00:14.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
   PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
   PCI: 00:15.0
   PCI: 00:16.0
   PCI: 00:16.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:17.0
   PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:17.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:17.0 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
   PCI: 00:18.0
   PCI: 00:18.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:18.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:18.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:18.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:18.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:18.0 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
   PCI: 00:1f.0
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index d9
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index da
   PCI: 00:1f.0 resource base fee00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index db
   PCI: 00:1f.0 resource base fed1c000 size 4000 align 14 gran 14 limit 0 flags f0000200 index dc
   PCI: 00:1f.3
   PCI: 00:1f.3 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
   PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffffffff flags 200 index 10
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 02:00.0 18 *  [0x0 - 0x1f] io
PCI: 00:03.0 compute_resources_io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:03.0 1c *  [0x0 - 0xfff] io
PCI: 00:14.0 18 *  [0x1000 - 0x101f] io
PCI: 00:14.1 18 *  [0x1020 - 0x103f] io
PCI: 00:14.2 18 *  [0x1040 - 0x105f] io
PCI: 00:14.3 18 *  [0x1060 - 0x107f] io
PCI: 00:17.0 20 *  [0x1080 - 0x109f] io
PCI: 00:18.0 20 *  [0x10a0 - 0x10bf] io
PCI: 00:17.0 10 *  [0x10c0 - 0x10c7] io
PCI: 00:17.0 18 *  [0x10c8 - 0x10cf] io
PCI: 00:18.0 10 *  [0x10d0 - 0x10d7] io
PCI: 00:18.0 18 *  [0x10d8 - 0x10df] io
PCI: 00:17.0 14 *  [0x10e0 - 0x10e3] io
PCI: 00:17.0 1c *  [0x10e4 - 0x10e7] io
PCI: 00:18.0 14 *  [0x10e8 - 0x10eb] io
PCI: 00:18.0 1c *  [0x10ec - 0x10ef] io
PCI_DOMAIN: 0000 compute_resources_io: base: 10f0 size: 10f0 align: 12 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.0 10 *  [0x0 - 0x1ffff] mem
PCI: 02:00.0 1c *  [0x20000 - 0x23fff] mem
PCI: 00:03.0 compute_resources_mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:03.0 20 *  [0x0 - 0xfffff] mem
PCI: 00:01.0 10 *  [0x100000 - 0x11ffff] mem
PCI: 00:03.0 10 *  [0x120000 - 0x13ffff] mem
PCI: 00:0b.0 18 *  [0x140000 - 0x15ffff] mem
PCI: 00:14.0 10 *  [0x160000 - 0x17ffff] mem
PCI: 00:14.1 10 *  [0x180000 - 0x19ffff] mem
PCI: 00:14.2 10 *  [0x1a0000 - 0x1bffff] mem
PCI: 00:14.3 10 *  [0x1c0000 - 0x1dffff] mem
PCI: 00:0b.0 20 *  [0x1e0000 - 0x1e3fff] mem
PCI: 00:14.0 20 *  [0x1e4000 - 0x1e7fff] mem
PCI: 00:14.1 20 *  [0x1e8000 - 0x1ebfff] mem
PCI: 00:14.2 20 *  [0x1ec000 - 0x1effff] mem
PCI: 00:14.3 20 *  [0x1f0000 - 0x1f3fff] mem
PCI: 00:17.0 24 *  [0x1f4000 - 0x1f47ff] mem
PCI: 00:18.0 24 *  [0x1f4800 - 0x1f4fff] mem
PCI: 00:13.0 10 *  [0x1f5000 - 0x1f53ff] mem
PCI: 00:16.0 10 *  [0x1f5400 - 0x1f57ff] mem
PCI: 00:1f.3 10 *  [0x1f5800 - 0x1f581f] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 1f5820 size: 1f5820 align: 20 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:03.0
constrain_resources: PCI: 02:00.0
constrain_resources: PCI: 00:0b.0
constrain_resources: PCI: 00:0e.0
constrain_resources: PCI: 00:0f.0
constrain_resources: PCI: 00:13.0
constrain_resources: PCI: 00:14.0
constrain_resources: PCI: 00:14.1
constrain_resources: PCI: 00:14.2
constrain_resources: PCI: 00:14.3
constrain_resources: PCI: 00:16.0
constrain_resources: PCI: 00:17.0
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:1f.0
constrain_resources: PCI: 00:1f.3
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
	lim->base 00001000 lim->limit 0000ef9f
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff
	lim->base 00000000 lim->limit dfffffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:10f0 align:12 gran:0 limit:ef9f
Assigned: PCI: 00:03.0 1c *  [0x1000 - 0x1fff] io
Assigned: PCI: 00:14.0 18 *  [0x2000 - 0x201f] io
Assigned: PCI: 00:14.1 18 *  [0x2020 - 0x203f] io
Assigned: PCI: 00:14.2 18 *  [0x2040 - 0x205f] io
Assigned: PCI: 00:14.3 18 *  [0x2060 - 0x207f] io
Assigned: PCI: 00:17.0 20 *  [0x2080 - 0x209f] io
Assigned: PCI: 00:18.0 20 *  [0x20a0 - 0x20bf] io
Assigned: PCI: 00:17.0 10 *  [0x20c0 - 0x20c7] io
Assigned: PCI: 00:17.0 18 *  [0x20c8 - 0x20cf] io
Assigned: PCI: 00:18.0 10 *  [0x20d0 - 0x20d7] io
Assigned: PCI: 00:18.0 18 *  [0x20d8 - 0x20df] io
Assigned: PCI: 00:17.0 14 *  [0x20e0 - 0x20e3] io
Assigned: PCI: 00:17.0 1c *  [0x20e4 - 0x20e7] io
Assigned: PCI: 00:18.0 14 *  [0x20e8 - 0x20eb] io
Assigned: PCI: 00:18.0 1c *  [0x20ec - 0x20ef] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 20f0 size: 10f0 align: 12 gran: 0 done
PCI: 00:01.0 allocate_resources_io: base:ef9f size:0 align:12 gran:12 limit:ef9f
PCI: 00:01.0 allocate_resources_io: next_base: ef9f size: 0 align: 12 gran: 12 done
PCI: 00:03.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ef9f
Assigned: PCI: 02:00.0 18 *  [0x1000 - 0x101f] io
PCI: 00:03.0 allocate_resources_io: next_base: 1020 size: 1000 align: 12 gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:dfe00000 size:1f5820 align:20 gran:0 limit:dfffffff
Assigned: PCI: 00:03.0 20 *  [0xdfe00000 - 0xdfefffff] mem
Assigned: PCI: 00:01.0 10 *  [0xdff00000 - 0xdff1ffff] mem
Assigned: PCI: 00:03.0 10 *  [0xdff20000 - 0xdff3ffff] mem
Assigned: PCI: 00:0b.0 18 *  [0xdff40000 - 0xdff5ffff] mem
Assigned: PCI: 00:14.0 10 *  [0xdff60000 - 0xdff7ffff] mem
Assigned: PCI: 00:14.1 10 *  [0xdff80000 - 0xdff9ffff] mem
Assigned: PCI: 00:14.2 10 *  [0xdffa0000 - 0xdffbffff] mem
Assigned: PCI: 00:14.3 10 *  [0xdffc0000 - 0xdffdffff] mem
Assigned: PCI: 00:0b.0 20 *  [0xdffe0000 - 0xdffe3fff] mem
Assigned: PCI: 00:14.0 20 *  [0xdffe4000 - 0xdffe7fff] mem
Assigned: PCI: 00:14.1 20 *  [0xdffe8000 - 0xdffebfff] mem
Assigned: PCI: 00:14.2 20 *  [0xdffec000 - 0xdffeffff] mem
Assigned: PCI: 00:14.3 20 *  [0xdfff0000 - 0xdfff3fff] mem
Assigned: PCI: 00:17.0 24 *  [0xdfff4000 - 0xdfff47ff] mem
Assigned: PCI: 00:18.0 24 *  [0xdfff4800 - 0xdfff4fff] mem
Assigned: PCI: 00:13.0 10 *  [0xdfff5000 - 0xdfff53ff] mem
Assigned: PCI: 00:16.0 10 *  [0xdfff5400 - 0xdfff57ff] mem
Assigned: PCI: 00:1f.3 10 *  [0xdfff5800 - 0xdfff581f] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: dfff5820 size: 1f5820 align: 20 gran: 0 done
PCI: 00:01.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:01.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:01.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:01.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:03.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:03.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:03.0 allocate_resources_mem: base:dfe00000 size:100000 align:20 gran:20 limit:dfffffff
Assigned: PCI: 02:00.0 10 *  [0xdfe00000 - 0xdfe1ffff] mem
Assigned: PCI: 02:00.0 1c *  [0xdfe20000 - 0xdfe23fff] mem
PCI: 00:03.0 allocate_resources_mem: next_base: dfe24000 size: 100000 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
Top of Low Used DRAM: 0x80000000
Top of Upper Used DRAM: 0x180000000
TSEG decoded, subtracting 2M
tseg_memory_base: 0x7fe00000
tseg_memory_size: 0x200000
Available memory: 2095104K (2046M)
Available memory above 4GB: 2048M
Adding PCIe config bar
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 cf <- [0x00e0000000 - 0x00e3ffffff] size 0x04000000 gran 0x00 mem<mmconfig>
PCI: 00:01.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 mem
PCI: 00:01.0 10 <- [0x00dff00000 - 0x00dff1ffff] size 0x00020000 gran 0x11 mem64
PCI: 00:03.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 02 io
PCI: 00:03.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:03.0 20 <- [0x00dfe00000 - 0x00dfefffff] size 0x00100000 gran 0x14 bus 02 mem
PCI: 00:03.0 10 <- [0x00dff20000 - 0x00dff3ffff] size 0x00020000 gran 0x11 mem64
PCI: 00:03.0 assign_resources, bus 2 link: 0
PCI: 02:00.0 10 <- [0x00dfe00000 - 0x00dfe1ffff] size 0x00020000 gran 0x11 mem
PCI: 02:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
PCI: 02:00.0 1c <- [0x00dfe20000 - 0x00dfe23fff] size 0x00004000 gran 0x0e mem
PCI: 00:03.0 assign_resources, bus 2 link: 0
PCI: 00:0b.0 18 <- [0x00dff40000 - 0x00dff5ffff] size 0x00020000 gran 0x11 mem64
PCI: 00:0b.0 20 <- [0x00dffe0000 - 0x00dffe3fff] size 0x00004000 gran 0x0e mem64
PCI: 00:13.0 10 <- [0x00dfff5000 - 0x00dfff53ff] size 0x00000400 gran 0x0a mem64
PCI: 00:14.0 10 <- [0x00dff60000 - 0x00dff7ffff] size 0x00020000 gran 0x11 mem64
PCI: 00:14.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
PCI: 00:14.0 20 <- [0x00dffe4000 - 0x00dffe7fff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.1 10 <- [0x00dff80000 - 0x00dff9ffff] size 0x00020000 gran 0x11 mem64
PCI: 00:14.1 18 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io
PCI: 00:14.1 20 <- [0x00dffe8000 - 0x00dffebfff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.2 10 <- [0x00dffa0000 - 0x00dffbffff] size 0x00020000 gran 0x11 mem64
PCI: 00:14.2 18 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io
PCI: 00:14.2 20 <- [0x00dffec000 - 0x00dffeffff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.3 10 <- [0x00dffc0000 - 0x00dffdffff] size 0x00020000 gran 0x11 mem64
PCI: 00:14.3 18 <- [0x0000002060 - 0x000000207f] size 0x00000020 gran 0x05 io
PCI: 00:14.3 20 <- [0x00dfff0000 - 0x00dfff3fff] size 0x00004000 gran 0x0e mem64
PCI: 00:16.0 10 <- [0x00dfff5400 - 0x00dfff57ff] size 0x00000400 gran 0x0a mem
PCI: 00:17.0 10 <- [0x00000020c0 - 0x00000020c7] size 0x00000008 gran 0x03 io
PCI: 00:17.0 14 <- [0x00000020e0 - 0x00000020e3] size 0x00000004 gran 0x02 io
PCI: 00:17.0 18 <- [0x00000020c8 - 0x00000020cf] size 0x00000008 gran 0x03 io
PCI: 00:17.0 1c <- [0x00000020e4 - 0x00000020e7] size 0x00000004 gran 0x02 io
PCI: 00:17.0 20 <- [0x0000002080 - 0x000000209f] size 0x00000020 gran 0x05 io
PCI: 00:17.0 24 <- [0x00dfff4000 - 0x00dfff47ff] size 0x00000800 gran 0x0b mem
PCI: 00:18.0 10 <- [0x00000020d0 - 0x00000020d7] size 0x00000008 gran 0x03 io
PCI: 00:18.0 14 <- [0x00000020e8 - 0x00000020eb] size 0x00000004 gran 0x02 io
PCI: 00:18.0 18 <- [0x00000020d8 - 0x00000020df] size 0x00000008 gran 0x03 io
PCI: 00:18.0 1c <- [0x00000020ec - 0x00000020ef] size 0x00000004 gran 0x02 io
PCI: 00:18.0 20 <- [0x00000020a0 - 0x00000020bf] size 0x00000020 gran 0x05 io
PCI: 00:18.0 24 <- [0x00dfff4800 - 0x00dfff4fff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x00dfff5800 - 0x00dfff581f] size 0x00000020 gran 0x05 mem
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 1000 size 10f0 align 12 gran 0 limit ef9f flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base dfe00000 size 1f5820 align 20 gran 0 limit dfffffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
  PCI_DOMAIN: 0000 resource base 100000 size 7fd00000 align 0 gran 0 limit 0 flags e0004200 index 4
  PCI_DOMAIN: 0000 resource base 7fe00000 size 200000 align 0 gran 0 limit 0 flags f0000200 index 6
  PCI_DOMAIN: 0000 resource base 100000000 size 80000000 align 0 gran 0 limit 0 flags e0004200 index 7
  PCI_DOMAIN: 0000 resource base e0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 8
  PCI_DOMAIN: 0000 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0200200 index 9
   PCI: 00:00.0
   PCI: 00:00.0 resource base e0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
   PCI: 00:01.0
   PCI: 00:01.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c
   PCI: 00:01.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
   PCI: 00:01.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20
   PCI: 00:01.0 resource base dff00000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 10
   PCI: 00:02.0
   PCI: 00:03.0 child on link 0 PCI: 02:00.0
   PCI: 00:03.0 resource base 1000 size 1000 align 12 gran 12 limit ef9f flags 60080102 index 1c
   PCI: 00:03.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
   PCI: 00:03.0 resource base dfe00000 size 100000 align 20 gran 20 limit dfffffff flags 60080202 index 20
   PCI: 00:03.0 resource base dff20000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 10
    PCI: 02:00.0
    PCI: 02:00.0 resource base dfe00000 size 20000 align 17 gran 17 limit dfffffff flags 60000200 index 10
    PCI: 02:00.0 resource base 1000 size 20 align 5 gran 5 limit ef9f flags 60000100 index 18
    PCI: 02:00.0 resource base dfe20000 size 4000 align 14 gran 14 limit dfffffff flags 60000200 index 1c
   PCI: 00:04.0
   PCI: 00:0b.0
   PCI: 00:0b.0 resource base dff40000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 18
   PCI: 00:0b.0 resource base dffe0000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 20
   PCI: 00:0e.0
   PCI: 00:0f.0
   PCI: 00:11.0
   PCI: 00:13.0
   PCI: 00:13.0 resource base dfff5000 size 400 align 10 gran 10 limit dfffffff flags 60000201 index 10
   PCI: 00:14.0
   PCI: 00:14.0 resource base dff60000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 10
   PCI: 00:14.0 resource base 2000 size 20 align 5 gran 5 limit ef9f flags 60000100 index 18
   PCI: 00:14.0 resource base dffe4000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 20
   PCI: 00:14.1
   PCI: 00:14.1 resource base dff80000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 10
   PCI: 00:14.1 resource base 2020 size 20 align 5 gran 5 limit ef9f flags 60000100 index 18
   PCI: 00:14.1 resource base dffe8000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 20
   PCI: 00:14.2
   PCI: 00:14.2 resource base dffa0000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 10
   PCI: 00:14.2 resource base 2040 size 20 align 5 gran 5 limit ef9f flags 60000100 index 18
   PCI: 00:14.2 resource base dffec000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 20
   PCI: 00:14.3
   PCI: 00:14.3 resource base dffc0000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 10
   PCI: 00:14.3 resource base 2060 size 20 align 5 gran 5 limit ef9f flags 60000100 index 18
   PCI: 00:14.3 resource base dfff0000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 20
   PCI: 00:15.0
   PCI: 00:16.0
   PCI: 00:16.0 resource base dfff5400 size 400 align 10 gran 10 limit dfffffff flags 60000200 index 10
   PCI: 00:17.0
   PCI: 00:17.0 resource base 20c0 size 8 align 3 gran 3 limit ef9f flags 60000100 index 10
   PCI: 00:17.0 resource base 20e0 size 4 align 2 gran 2 limit ef9f flags 60000100 index 14
   PCI: 00:17.0 resource base 20c8 size 8 align 3 gran 3 limit ef9f flags 60000100 index 18
   PCI: 00:17.0 resource base 20e4 size 4 align 2 gran 2 limit ef9f flags 60000100 index 1c
   PCI: 00:17.0 resource base 2080 size 20 align 5 gran 5 limit ef9f flags 60000100 index 20
   PCI: 00:17.0 resource base dfff4000 size 800 align 11 gran 11 limit dfffffff flags 60000200 index 24
   PCI: 00:18.0
   PCI: 00:18.0 resource base 20d0 size 8 align 3 gran 3 limit ef9f flags 60000100 index 10
   PCI: 00:18.0 resource base 20e8 size 4 align 2 gran 2 limit ef9f flags 60000100 index 14
   PCI: 00:18.0 resource base 20d8 size 8 align 3 gran 3 limit ef9f flags 60000100 index 18
   PCI: 00:18.0 resource base 20ec size 4 align 2 gran 2 limit ef9f flags 60000100 index 1c
   PCI: 00:18.0 resource base 20a0 size 20 align 5 gran 5 limit ef9f flags 60000100 index 20
   PCI: 00:18.0 resource base dfff4800 size 800 align 11 gran 11 limit dfffffff flags 60000200 index 24
   PCI: 00:1f.0
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index d9
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index da
   PCI: 00:1f.0 resource base fee00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index db
   PCI: 00:1f.0 resource base fed1c000 size 4000 align 14 gran 14 limit 0 flags f0000200 index dc
   PCI: 00:1f.3
   PCI: 00:1f.3 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
   PCI: 00:1f.3 resource base dfff5800 size 20 align 5 gran 5 limit dfffffff flags 60000200 index 10
Done allocating resources.
Enabling resources...
PCI: 00:00.0 subsystem <- 0000/0000
PCI: 00:00.0 cmd <- 07
PCI: 00:01.0 bridge ctrl <- 0003
PCI: 00:01.0 cmd <- 02
PCI: 00:03.0 bridge ctrl <- 0003
PCI: 00:03.0 cmd <- 07
PCI: 00:0b.0 cmd <- 02
PCI: 00:0e.0 cmd <- 00
PCI: 00:0f.0 cmd <- 04
PCI: 00:13.0 subsystem <- 0000/0000
PCI: 00:13.0 cmd <- 06
PCI: 00:14.0 cmd <- 07
PCI: 00:14.1 cmd <- 03
PCI: 00:14.2 cmd <- 03
PCI: 00:14.3 cmd <- 03
PCI: 00:16.0 subsystem <- 0000/0000
PCI: 00:16.0 cmd <- 02
PCI: 00:17.0 subsystem <- 0000/0000
PCI: 00:17.0 cmd <- 03
PCI: 00:18.0 subsystem <- 0000/0000
PCI: 00:18.0 cmd <- 03
PCI: 00:1f.0 subsystem <- 0000/0000
PCI: 00:1f.0 cmd <- 07
PCI: 00:1f.3 subsystem <- 0000/0000
PCI: 00:1f.3 cmd <- 03
PCI: 02:00.0 cmd <- 03
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x00001000, code_size=0x00000031
Initializing CPU #0
CPU: vendor Intel device 406d8
CPU: family 06, model 4d, stepping 08
Enabling cache
CBFS: Looking for 'cpu_microcode_blob.bin'
CBFS: found.
microcode: sig=0x406d8 pf=0x1 revision=0x112
microcode: updated to revision 0x11d date=2013-10-29
CPU: Intel(R) Atom(TM) CPU  C2558  @ 2.40GHz.

Setting fixed MTRRs(0-88) Type: UC
Setting fixed MTRRs(0-16) Type: WB
DONE fixed MTRRs
call enable_fixed_mtrr()
CPU physical address size: 36 bits
Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
Setting variable MTRR 1, base: 4096MB, range: 2048MB, type WB
Setting variable MTRR 2, base: 2046MB, range:    2MB, type UC
Setting variable MTRR 3, base: 2048MB, range: 2048MB, type UC
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x00 done.
CPU: 0 has 4 cores 1 threads
CPU: 0 has core 2
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 2.
After apic_write.
Initializing CPU #1
Startup point 1.
Waiting for send to finish...
+CPU: vendor Intel device 406d8
Sending STARTUP #2 to 2.
After apic_write.
CPU: family 06, model 4d, stepping 08
Startup point 1.
Waiting for send to finish...
+Enabling cache
After Startup.
CBFS: Looking for 'cpu_microcode_blob.bin'
CPU: 0 has core 4
CBFS: found.
Asserting INIT.
Waiting for send to finish...
+microcode: sig=0x406d8 pf=0x1 revision=0x11d
microcode: updated to revision 0x11d date=2013-10-29
CPU: Intel(R) Atom(TM) CPU  C2558  @ 2.40GHz.

Setting fixed MTRRs(0-88) Type: UC
Deasserting INIT.
Waiting for send to finish...
+Setting fixed MTRRs(0-16) Type: WB
#startup loops: 2.
Sending STARTUP #1 to 4.
DONE fixed MTRRs
call enable_fixed_mtrr()
After apic_write.
CPU physical address size: 36 bits
Startup point 1.
Waiting for send to finish...
+Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
Sending STARTUP #2 to 4.
Setting variable MTRR 1, base: 4096MB, range: 2048MB, type WB
After apic_write.
Setting variable MTRR 2, base: 2046MB, range:    2MB, type UC
Startup point 1.
Waiting for send to finish...
+Setting variable MTRR 3, base: 2048MB, range: 2048MB, type UC
After Startup.
DONE variable MTRRs
Clear out the extra MTRR's
CPU: 0 has core 6
call enable_var_mtrr()
Asserting INIT.
Leave x86_setup_var_mtrrs
Waiting for send to finish...
+
MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Initializing CPU #2
Setting up local apic...CPU: vendor Intel device 406d8
 apic_id: 0x02 done.
CPU: family 06, model 4d, stepping 08
CPU #1 initialized
Deasserting INIT.
Waiting for send to finish...
+Enabling cache
#startup loops: 2.
Sending STARTUP #1 to 6.
CBFS: Looking for 'cpu_microcode_blob.bin'
After apic_write.
CBFS: found.
Startup point 1.
Waiting for send to finish...
+microcode: sig=0x406d8 pf=0x1 revision=0x112
Sending STARTUP #2 to 6.
microcode: updated to revision 0x11d date=2013-10-29
After apic_write.
CPU: Intel(R) Atom(TM) CPU  C2558  @ 2.40GHz.
Startup point 1.
Waiting for send to finish...
+
Setting fixed MTRRs(0-88) Type: UC
After Startup.
Setting fixed MTRRs(0-16) Type: WB
CPU #0 initialized
Waiting for 2 CPUS to stop
DONE fixed MTRRs
call enable_fixed_mtrr()
Initializing CPU #3
CPU physical address size: 36 bits
CPU: vendor Intel device 406d8
Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
CPU: family 06, model 4d, stepping 08
Setting variable MTRR 1, base: 4096MB, range: 2048MB, type WB
Enabling cache
Setting variable MTRR 2, base: 2046MB, range:    2MB, type UC
CBFS: Looking for 'cpu_microcode_blob.bin'
Setting variable MTRR 3, base: 2048MB, range: 2048MB, type UC
CBFS: found.
DONE variable MTRRs
Clear out the extra MTRR's
microcode: sig=0x406d8 pf=0x1 revision=0x11d
call enable_var_mtrr()
microcode: updated to revision 0x11d date=2013-10-29
Leave x86_setup_var_mtrrs
CPU: Intel(R) Atom(TM) CPU  C2558  @ 2.40GHz.

Setting fixed MTRRs(0-88) Type: UC

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting fixed MTRRs(0-16) Type: WB
Setting up local apic...DONE fixed MTRRs
call enable_fixed_mtrr()
 apic_id: 0x04 done.
CPU physical address size: 36 bits
CPU #2 initialized
Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
Waiting for 1 CPUS to stop
Setting variable MTRR 1, base: 4096MB, range: 2048MB, type WB
Setting variable MTRR 2, base: 2046MB, range:    2MB, type UC
Setting variable MTRR 3, base: 2048MB, range: 2048MB, type UC
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x06 done.
CPU #3 initialized
All AP CPUs stopped (7046 loops)
PCI: 00:01.0 init
PCI: 00:03.0 init
PCI: 00:0b.0 init
PCI: 00:0e.0 init
PCI: 00:0f.0 init
PCI: 00:13.0 init
PCI: 00:14.0 init
PCI: 00:14.1 init
PCI: 00:14.2 init
PCI: 00:14.3 init
PCI: 00:16.0 init
EHCI: Setting up controller.. done.
PCI: 00:17.0 init
SATA: Initializing...
SATA: Controller in AHCI mode.
ABAR: DFFF4000
PCI: 00:18.0 init
SATA3: Initializing...
SATA3: Controller in AHCI mode.
ABAR: DFFF4800
PCI: 00:1f.0 init
Rangeley: lpc_init
PCI: 00:1f.3 init
PCI: 02:00.0 init
Devices initialized
Show all devs...After init.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 0
PCI: 00:03.0: enabled 1
PCI: 00:04.0: enabled 0
PCI: 00:11.0: enabled 0
PCI: 00:15.0: enabled 0
PCI: 00:13.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:17.0: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.3: enabled 1
PCI: 00:0b.0: enabled 1
PCI: 00:0e.0: enabled 1
PCI: 00:0f.0: enabled 1
PCI: 00:14.0: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PCI: 02:00.0: enabled 1
APIC: 02: enabled 1
APIC: 04: enabled 1
APIC: 06: enabled 1
Re-Initializing CBMEM area to 0x7fde0000
Adding CBMEM entry as no. 2
Moving GDT to 7fde2600...ok
Updating MRC cache data.
picked entry 1 from cache block
SF: Detected W25Q64 with page size 1000, total 800000
picked entry 2 from cache block when looking for empty block
Finally: write MRC cache update to flash
SF: Winbond: Successfully programmed 8848 bytes @ 0x776000
High Tables Base is 7fde0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 3
Copying Interrupt Routing Table to 0x7fde2800... done.
PIRQ table: 320 bytes.
Wrote the mp table end at: 000f0410 - 000f059c
Adding CBMEM entry as no. 4
Wrote the mp table end at: 7fde3810 - 7fde399c
MP table: 412 bytes.
Adding CBMEM entry as no. 5
smbios_write_tables: 7fde4800
Root Device (Intel Mohon Peak platform)
APIC_CLUSTER: 0 (Intel Rangeley Northbridge)
APIC: 00 (Socket rPGA989 CPU)
PCI_DOMAIN: 0000 (Intel Rangeley Northbridge)
PCI: 00:00.0 (Intel Rangeley Northbridge)
PCI: 00:01.0 (Intel Rangeley Northbridge)
PCI: 00:02.0 (Intel Rangeley Northbridge)
PCI: 00:03.0 (Intel Rangeley Northbridge)
PCI: 00:04.0 (Intel Rangeley Northbridge)
PCI: 00:11.0 (Intel Rangeley Southbridge)
PCI: 00:15.0 (Intel Rangeley Southbridge)
PCI: 00:13.0 (Intel Rangeley Southbridge)
PCI: 00:16.0 (Intel Rangeley Southbridge)
PCI: 00:17.0 (Intel Rangeley Southbridge)
PCI: 00:18.0 (Intel Rangeley Southbridge)
PCI: 00:1f.0 (Intel Rangeley Southbridge)
PCI: 00:1f.3 (Intel Rangeley Southbridge)
PCI: 00:0b.0 ()
PCI: 00:0e.0 ()
PCI: 00:0f.0 ()
PCI: 00:14.0 ()
PCI: 00:14.1 ()
PCI: 00:14.2 ()
PCI: 00:14.3 ()
PCI: 02:00.0 ()
APIC: 02 ()
APIC: 04 ()
APIC: 06 ()
SMBIOS tables: 295 bytes.
Adding CBMEM entry as no. 6
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 3000
New low_table_end: 0x00000528
Now going to write high coreboot table at 0x7fde5000
rom_table_end = 0x7fde5000
Adjust low_table_end from 0x00000528 to 0x00001000 
Adjust rom_table_end from 0x7fde5000 to 0x7fdf0000 
Adding high table area
coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000a0000-00000000000fffff: RESERVED
 3. 0000000000100000-000000007fddffff: RAM
 4. 000000007fde0000-000000007fdfffff: CONFIGURATION TABLES
 5. 000000007fe00000-000000007fffffff: RESERVED
 6. 00000000e0000000-00000000e3ffffff: RESERVED
 7. 00000000fec00000-00000000fec00fff: RESERVED
 8. 00000000fed1c000-00000000fed1ffff: RESERVED
 9. 00000000fee00000-00000000fee00fff: RESERVED
10. 00000000ff800000-00000000ffffffff: RESERVED
11. 0000000100000000-000000017fffffff: RAM
Wrote coreboot table at: 7fde5000, 0x23c bytes, checksum 9457
coreboot table: 596 bytes.
Multiboot Information structure has been written.
 0. FREE SPACE 7fded000 00013000
 1. MRC DATA   7fde0200 00002400
 2. GDT        7fde2600 00000200
 3. IRQ TABLE  7fde2800 00001000
 4. SMP TABLE  7fde3800 00001000
 5. SMBIOS     7fde4800 00000800
 6. COREBOOT   7fde5000 00008000
CBFS: Looking for 'fallback/payload'
CBFS: found.
Got a payload
CPU0: stack from 00198000 to 001a0000:Lowest stack address 0019fb28
Loading segment from rom address 0xffc6caf8
  code (compression=1)
  New segment dstaddr 0xe4350 memsize 0x1bcb0 srcaddr 0xffc6cb30 filesize 0xe50c
  (cleaned up) New segment addr 0xe4350 size 0x1bcb0 offset 0xffc6cb30 filesize 0xe50c
Loading segment from rom address 0xffc6cb14
  Entry Point 0x00000000
Payload (probably SeaBIOS) loaded into a reserved area in the lower 1MB
Loading Segment: addr: 0x00000000000e4350 memsz: 0x000000000001bcb0 filesz: 0x000000000000e50c
lb: [0x0000000000100000, 0x00000000001a4000)
Post relocation: addr: 0x00000000000e4350 memsz: 0x000000000001bcb0 filesz: 0x000000000000e50c
using LZMA
[ 0x000e4350, 00100000, 0x00100000) <- ffc6cb30
dest 000e4350, end 00100000, bouncebuffer 7fc98000
Loaded segments
Jumping to boot code at fd567
entry    = 0x000fd567
lb_start = 0x00100000
lb_size  = 0x000a4000
adjust   = 0x7fc3c000
buffer   = 0x7fc98000
     elf_boot_notes = 0x001185b4
adjusted_boot_notes = 0x7fd545b4


coreboot-unknown Thu Jul 10 16:15:02 EDT 2014 starting...
picked entry 2 from cache block
MRC cache present at fff76000.
FSP NVRAM Hob at 0x2275d8 (size = 0x2280).
Re-Initializing CBMEM area to 0x7fde0000
Initializing CBMEM area to 0x7fde0000 (131072 bytes)
Adding CBMEM entry as no. 1
Relocate MRC DATA from 002275d8 to 7fde0200 (8832 bytes)
Setting up static southbridge registers...
Setting up graphic registers...
Loading image.
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (671744 bytes), entry @ 0x100000
Jumping to image.
coreboot-unknown Thu Jul 10 16:15:02 EDT 2014 booting...
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:17.0: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.3: enabled 1
Compare with tree...
Root Device: enabled 1
 APIC_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 PCI_DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:01.0: enabled 1
  PCI: 00:02.0: enabled 1
  PCI: 00:03.0: enabled 1
  PCI: 00:04.0: enabled 1
  PCI: 00:11.0: enabled 1
  PCI: 00:15.0: enabled 1
  PCI: 00:13.0: enabled 1
  PCI: 00:16.0: enabled 1
  PCI: 00:17.0: enabled 1
  PCI: 00:18.0: enabled 1
  PCI: 00:1f.0: enabled 1
  PCI: 00:1f.3: enabled 1
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0000] ops
PCI: 00:00.0 [8086/1f0b] enabled
PCI: 00:01.0 [8086/0000] bus ops
PCI: 00:01.0 [8086/1f10] enabled
PCI: Static device PCI: 00:02.0 not found, disabling it. id read=0xffffffff
PCI: 00:03.0 [8086/0000] bus ops
PCI: 00:03.0 [8086/1f12] enabled
PCI: Static device PCI: 00:04.0 not found, disabling it. id read=0xffffffff
PCI: 00:0b.0 [8086/1f18] enabled
PCI: 00:0e.0 [8086/1f14] enabled
PCI: 00:0f.0 [8086/1f16] enabled
PCI: Static device PCI: 00:11.0 not found, disabling it. id read=0xffffffff
PCI: 00:13.0 [8086/1f15] enabled
PCI: 00:14.0 [8086/1f41] enabled
PCI: 00:14.1 [8086/1f41] enabled
PCI: 00:14.2 [8086/1f41] enabled
PCI: 00:14.3 [8086/1f41] enabled
PCI: Static device PCI: 00:15.0 not found, disabling it. id read=0xffffffff
PCI: 00:16.0 [8086/0000] ops
PCI: 00:16.0 [8086/1f2c] enabled
PCI: 00:17.0 [8086/0000] ops
PCI: 00:17.0 [8086/1f22] enabled
PCI: 00:18.0 [8086/0000] ops
PCI: 00:18.0 [8086/1f32] enabled
PCI: 00:1f.0 [8086/0000] bus ops
PCI: 00:1f.0 [8086/1f38] enabled
PCI: 00:1f.3 [8086/0000] bus ops
PCI: 00:1f.3 [8086/1f3c] enabled
[ww] do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
[ww] do_pci_scan_bridge for PCI: 00:03.0
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [8086/1539] enabled
PCI: pci_scan_bus returning with max=002
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x11 @ 0x70
Capability: type 0x10 @ 0xa0
Capability: type 0x10 @ 0x40
do_pci_scan_bridge returns max 2
scan_static_bus for PCI: 00:1f.0
scan_static_bus for PCI: 00:1f.0 done
scan_static_bus for PCI: 00:1f.3
scan_static_bus for PCI: 00:1f.3 done
PCI: pci_scan_bus returning with max=002
scan_static_bus for Root Device done
done
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
Adding PCIe enhanced config space BAR 0xe0000000-0xe4000000.
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:03.0 read_resources bus 2 link: 0
PCI: 00:03.0 read_resources bus 2 link: 0 done
rangeley_lpc_read_resources
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000


coreboot-unknown Thu Jul 10 16:15:02 EDT 2014 starting...
picked entry 2 from cache block
MRC cache present at fff76000.


coreboot-unknown Thu Jul 10 16:15:02 EDT 2014 starting...
picked entry 2 from cache block
MRC cache present at fff76000.
FSP NVRAM Hob at 0x2275d8 (size = 0x2280).
Re-Initializing CBMEM area to 0x7fde0000
Initializing CBMEM area to 0x7fde0000 (131072 bytes)
Adding CBMEM entry as no. 1
Relocate MRC DATA from 002275d8 to 7fde0200 (8832 bytes)
Setting up static southbridge registers...
Setting up graphic registers...
Loading image.
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (671744 bytes), entry @ 0x100000
Jumping to image.
coreboot-unknown Thu Jul 10 16:15:02 EDT 2014 booting...
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:17.0: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.3: enabled 1
Compare with tree...
Root Device: enabled 1
 APIC_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 PCI_DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:01.0: enabled 1
  PCI: 00:02.0: enabled 1
  PCI: 00:03.0: enabled 1
  PCI: 00:04.0: enabled 1
  PCI: 00:11.0: enabled 1
  PCI: 00:15.0: enabled 1
  PCI: 00:13.0: enabled 1
  PCI: 00:16.0: enabled 1
  PCI: 00:17.0: enabled 1
  PCI: 00:18.0: enabled 1
  PCI: 00:1f.0: enabled 1
  PCI: 00:1f.3: enabled 1
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0000] ops
PCI: 00:00.0 [8086/1f0b] enabled
PCI: 00:01.0 [8086/0000] bus ops
PCI: 00:01.0 [8086/1f10] enabled
PCI: Static device PCI: 00:02.0 not found, disabling it. id read=0xffffffff
PCI: 00:03.0 [8086/0000] bus ops
PCI: 00:03.0 [8086/1f12] enabled
PCI: Static device PCI: 00:04.0 not found, disabling it. id read=0xffffffff
PCI: 00:0b.0 [8086/1f18] enabled
PCI: 00:0e.0 [8086/1f14] enabled
PCI: 00:0f.0 [8086/1f16] enabled
PCI: Static device PCI: 00:11.0 not found, disabling it. id read=0xffffffff
PCI: 00:13.0 [8086/1f15] enabled
PCI: 00:14.0 [8086/1f41] enabled
PCI: 00:14.1 [8086/1f41] enabled
PCI: 00:14.2 [8086/1f41] enabled
PCI: 00:14.3 [8086/1f41] enabled
PCI: Static device PCI: 00:15.0 not found, disabling it. id read=0xffffffff
PCI: 00:16.0 [8086/0000] ops
PCI: 00:16.0 [8086/1f2c] enabled
PCI: 00:17.0 [8086/0000] ops
PCI: 00:17.0 [8086/1f22] enabled
PCI: 00:18.0 [8086/0000] ops
PCI: 00:18.0 [8086/1f32] enabled
PCI: 00:1f.0 [8086/0000] bus ops
PCI: 00:1f.0 [8086/1f38] enabled
PCI: 00:1f.3 [8086/0000] bus ops
PCI: 00:1f.3 [8086/1f3c] enabled
[ww] do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
[ww] do_pci_scan_bridge for PCI: 00:03.0
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [8086/1539] enabled
PCI: pci_scan_bus returning with max=002
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x11 @ 0x70
Capability: type 0x10 @ 0xa0
Capability: type 0x10 @ 0x40
do_pci_scan_bridge returns max 2
scan_static_bus for PCI: 00:1f.0
scan_static_bus for PCI: 00:1f.0 done
scan_static_bus for PCI: 00:1f.3
scan_static_bus for PCI: 00:1f.3 done
PCI: pci_scan_bus returning with max=002
scan_static_bus for Root Device done
done
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
Adding PCIe enhanced config space BAR 0xe0000000-0xe4000000.
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:03.0 read_resources bus 2 link: 0
PCI: 00:03.0 read_resources bus 2 link: 0 done
rangeley_lpc_read_resources
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:00.0 resource base e0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
   PCI: 00:01.0
   PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
   PCI: 00:02.0
   PCI: 00:03.0 child on link 0 PCI: 02:00.0
   PCI: 00:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:03.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
    PCI: 02:00.0
    PCI: 02:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
    PCI: 02:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
    PCI: 02:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
   PCI: 00:04.0
   PCI: 00:0b.0
   PCI: 00:0b.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 18
   PCI: 00:0b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
   PCI: 00:0e.0
   PCI: 00:0f.0
   PCI: 00:11.0
   PCI: 00:13.0
   PCI: 00:13.0 resource base 0 size 400 align 10 gran 10 limit ffffffffffffffff flags 201 index 10
   PCI: 00:14.0
   PCI: 00:14.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
   PCI: 00:14.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
   PCI: 00:14.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
   PCI: 00:14.1
   PCI: 00:14.1 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
   PCI: 00:14.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
   PCI: 00:14.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
   PCI: 00:14.2
   PCI: 00:14.2 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
   PCI: 00:14.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
   PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
   PCI: 00:14.3
   PCI: 00:14.3 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
   PCI: 00:14.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
   PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
   PCI: 00:15.0
   PCI: 00:16.0
   PCI: 00:16.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:17.0
   PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:17.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:17.0 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
   PCI: 00:18.0
   PCI: 00:18.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:18.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:18.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:18.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:18.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:18.0 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
   PCI: 00:1f.0
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index d9
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index da
   PCI: 00:1f.0 resource base fee00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index db
   PCI: 00:1f.0 resource base fed1c000 size 4000 align 14 gran 14 limit 0 flags f0000200 index dc
   PCI: 00:1f.3
   PCI: 00:1f.3 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
   PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffffffff flags 200 index 10
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 02:00.0 18 *  [0x0 - 0x1f] io
PCI: 00:03.0 compute_resources_io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:03.0 1c *  [0x0 - 0xfff] io
PCI: 00:14.0 18 *  [0x1000 - 0x101f] io
PCI: 00:14.1 18 *  [0x1020 - 0x103f] io
PCI: 00:14.2 18 *  [0x1040 - 0x105f] io
PCI: 00:14.3 18 *  [0x1060 - 0x107f] io
PCI: 00:17.0 20 *  [0x1080 - 0x109f] io
PCI: 00:18.0 20 *  [0x10a0 - 0x10bf] io
PCI: 00:17.0 10 *  [0x10c0 - 0x10c7] io
PCI: 00:17.0 18 *  [0x10c8 - 0x10cf] io
PCI: 00:18.0 10 *  [0x10d0 - 0x10d7] io
PCI: 00:18.0 18 *  [0x10d8 - 0x10df] io
PCI: 00:17.0 14 *  [0x10e0 - 0x10e3] io
PCI: 00:17.0 1c *  [0x10e4 - 0x10e7] io
PCI: 00:18.0 14 *  [0x10e8 - 0x10eb] io
PCI: 00:18.0 1c *  [0x10ec - 0x10ef] io
PCI_DOMAIN: 0000 compute_resources_io: base: 10f0 size: 10f0 align: 12 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.0 10 *  [0x0 - 0x1ffff] mem
PCI: 02:00.0 1c *  [0x20000 - 0x23fff] mem
PCI: 00:03.0 compute_resources_mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:03.0 20 *  [0x0 - 0xfffff] mem
PCI: 00:01.0 10 *  [0x100000 - 0x11ffff] mem
PCI: 00:03.0 10 *  [0x120000 - 0x13ffff] mem
PCI: 00:0b.0 18 *  [0x140000 - 0x15ffff] mem
PCI: 00:14.0 10 *  [0x160000 - 0x17ffff] mem
PCI: 00:14.1 10 *  [0x180000 - 0x19ffff] mem
PCI: 00:14.2 10 *  [0x1a0000 - 0x1bffff] mem
PCI: 00:14.3 10 *  [0x1c0000 - 0x1dffff] mem
PCI: 00:0b.0 20 *  [0x1e0000 - 0x1e3fff] mem
PCI: 00:14.0 20 *  [0x1e4000 - 0x1e7fff] mem
PCI: 00:14.1 20 *  [0x1e8000 - 0x1ebfff] mem
PCI: 00:14.2 20 *  [0x1ec000 - 0x1effff] mem
PCI: 00:14.3 20 *  [0x1f0000 - 0x1f3fff] mem
PCI: 00:17.0 24 *  [0x1f4000 - 0x1f47ff] mem
PCI: 00:18.0 24 *  [0x1f4800 - 0x1f4fff] mem
PCI: 00:13.0 10 *  [0x1f5000 - 0x1f53ff] mem
PCI: 00:16.0 10 *  [0x1f5400 - 0x1f57ff] mem
PCI: 00:1f.3 10 *  [0x1f5800 - 0x1f581f] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 1f5820 size: 1f5820 align: 20 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:03.0
constrain_resources: PCI: 02:00.0
constrain_resources: PCI: 00:0b.0
constrain_resources: PCI: 00:0e.0
constrain_resources: PCI: 00:0f.0
constrain_resources: PCI: 00:13.0
constrain_resources: PCI: 00:14.0
constrain_resources: PCI: 00:14.1
constrain_resources: PCI: 00:14.2
constrain_resources: PCI: 00:14.3
constrain_resources: PCI: 00:16.0
constrain_resources: PCI: 00:17.0
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:1f.0
constrain_resources: PCI: 00:1f.3
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
	lim->base 00001000 lim->limit 0000ef9f
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff
	lim->base 00000000 lim->limit dfffffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:10f0 align:12 gran:0 limit:ef9f
Assigned: PCI: 00:03.0 1c *  [0x1000 - 0x1fff] io
Assigned: PCI: 00:14.0 18 *  [0x2000 - 0x201f] io
Assigned: PCI: 00:14.1 18 *  [0x2020 - 0x203f] io
Assigned: PCI: 00:14.2 18 *  [0x2040 - 0x205f] io
Assigned: PCI: 00:14.3 18 *  [0x2060 - 0x207f] io
Assigned: PCI: 00:17.0 20 *  [0x2080 - 0x209f] io
Assigned: PCI: 00:18.0 20 *  [0x20a0 - 0x20bf] io
Assigned: PCI: 00:17.0 10 *  [0x20c0 - 0x20c7] io
Assigned: PCI: 00:17.0 18 *  [0x20c8 - 0x20cf] io
Assigned: PCI: 00:18.0 10 *  [0x20d0 - 0x20d7] io
Assigned: PCI: 00:18.0 18 *  [0x20d8 - 0x20df] io
Assigned: PCI: 00:17.0 14 *  [0x20e0 - 0x20e3] io
Assigned: PCI: 00:17.0 1c *  [0x20e4 - 0x20e7] io
Assigned: PCI: 00:18.0 14 *  [0x20e8 - 0x20eb] io
Assigned: PCI: 00:18.0 1c *  [0x20ec - 0x20ef] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 20f0 size: 10f0 align: 12 gran: 0 done
PCI: 00:01.0 allocate_resources_io: base:ef9f size:0 align:12 gran:12 limit:ef9f
PCI: 00:01.0 allocate_resources_io: next_base: ef9f size: 0 align: 12 gran: 12 done
PCI: 00:03.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ef9f
Assigned: PCI: 02:00.0 18 *  [0x1000 - 0x101f] io
PCI: 00:03.0 allocate_resources_io: next_base: 1020 size: 1000 align: 12 gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:dfe00000 size:1f5820 align:20 gran:0 limit:dfffffff
Assigned: PCI: 00:03.0 20 *  [0xdfe00000 - 0xdfefffff] mem
Assigned: PCI: 00:01.0 10 *  [0xdff00000 - 0xdff1ffff] mem
Assigned: PCI: 00:03.0 10 *  [0xdff20000 - 0xdff3ffff] mem
Assigned: PCI: 00:0b.0 18 *  [0xdff40000 - 0xdff5ffff] mem
Assigned: PCI: 00:14.0 10 *  [0xdff60000 - 0xdff7ffff] mem
Assigned: PCI: 00:14.1 10 *  [0xdff80000 - 0xdff9ffff] mem
Assigned: PCI: 00:14.2 10 *  [0xdffa0000 - 0xdffbffff] mem
Assigned: PCI: 00:14.3 10 *  [0xdffc0000 - 0xdffdffff] mem
Assigned: PCI: 00:0b.0 20 *  [0xdffe0000 - 0xdffe3fff] mem
Assigned: PCI: 00:14.0 20 *  [0xdffe4000 - 0xdffe7fff] mem
Assigned: PCI: 00:14.1 20 *  [0xdffe8000 - 0xdffebfff] mem
Assigned: PCI: 00:14.2 20 *  [0xdffec000 - 0xdffeffff] mem
Assigned: PCI: 00:14.3 20 *  [0xdfff0000 - 0xdfff3fff] mem
Assigned: PCI: 00:17.0 24 *  [0xdfff4000 - 0xdfff47ff] mem
Assigned: PCI: 00:18.0 24 *  [0xdfff4800 - 0xdfff4fff] mem
Assigned: PCI: 00:13.0 10 *  [0xdfff5000 - 0xdfff53ff] mem
Assigned: PCI: 00:16.0 10 *  [0xdfff5400 - 0xdfff57ff] mem
Assigned: PCI: 00:1f.3 10 *  [0xdfff5800 - 0xdfff581f] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: dfff5820 size: 1f5820 align: 20 gran: 0 done
PCI: 00:01.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:01.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:01.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:01.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:03.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:03.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:03.0 allocate_resources_mem: base:dfe00000 size:100000 align:20 gran:20 limit:dfffffff
Assigned: PCI: 02:00.0 10 *  [0xdfe00000 - 0xdfe1ffff] mem
Assigned: PCI: 02:00.0 1c *  [0xdfe20000 - 0xdfe23fff] mem
PCI: 00:03.0 allocate_resources_mem: next_base: dfe24000 size: 100000 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
Top of Low Used DRAM: 0x80000000
Top of Upper Used DRAM: 0x180000000
TSEG decoded, subtracting 2M
tseg_memory_base: 0x7fe00000
tseg_memory_size: 0x200000
Available memory: 2095104K (2046M)
Available memory above 4GB: 2048M
Adding PCIe config bar
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 cf <- [0x00e0000000 - 0x00e3ffffff] size 0x04000000 gran 0x00 mem<mmconfig>
PCI: 00:01.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 mem
PCI: 00:01.0 10 <- [0x00dff00000 - 0x00dff1ffff] size 0x00020000 gran 0x11 mem64
PCI: 00:03.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 02 io
PCI: 00:03.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:03.0 20 <- [0x00dfe00000 - 0x00dfefffff] size 0x00100000 gran 0x14 bus 02 mem
PCI: 00:03.0 10 <- [0x00dff20000 - 0x00dff3ffff] size 0x00020000 gran 0x11 mem64
PCI: 00:03.0 assign_resources, bus 2 link: 0
PCI: 02:00.0 10 <- [0x00dfe00000 - 0x00dfe1ffff] size 0x00020000 gran 0x11 mem
PCI: 02:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
PCI: 02:00.0 1c <- [0x00dfe20000 - 0x00dfe23fff] size 0x00004000 gran 0x0e mem
PCI: 00:03.0 assign_resources, bus 2 link: 0
PCI: 00:0b.0 18 <- [0x00dff40000 - 0x00dff5ffff] size 0x00020000 gran 0x11 mem64
PCI: 00:0b.0 20 <- [0x00dffe0000 - 0x00dffe3fff] size 0x00004000 gran 0x0e mem64
PCI: 00:13.0 10 <- [0x00dfff5000 - 0x00dfff53ff] size 0x00000400 gran 0x0a mem64
PCI: 00:14.0 10 <- [0x00dff60000 - 0x00dff7ffff] size 0x00020000 gran 0x11 mem64
PCI: 00:14.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
PCI: 00:14.0 20 <- [0x00dffe4000 - 0x00dffe7fff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.1 10 <- [0x00dff80000 - 0x00dff9ffff] size 0x00020000 gran 0x11 mem64
PCI: 00:14.1 18 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io
PCI: 00:14.1 20 <- [0x00dffe8000 - 0x00dffebfff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.2 10 <- [0x00dffa0000 - 0x00dffbffff] size 0x00020000 gran 0x11 mem64
PCI: 00:14.2 18 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io
PCI: 00:14.2 20 <- [0x00dffec000 - 0x00dffeffff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.3 10 <- [0x00dffc0000 - 0x00dffdffff] size 0x00020000 gran 0x11 mem64
PCI: 00:14.3 18 <- [0x0000002060 - 0x000000207f] size 0x00000020 gran 0x05 io
PCI: 00:14.3 20 <- [0x00dfff0000 - 0x00dfff3fff] size 0x00004000 gran 0x0e mem64
PCI: 00:16.0 10 <- [0x00dfff5400 - 0x00dfff57ff] size 0x00000400 gran 0x0a mem
PCI: 00:17.0 10 <- [0x00000020c0 - 0x00000020c7] size 0x00000008 gran 0x03 io
PCI: 00:17.0 14 <- [0x00000020e0 - 0x00000020e3] size 0x00000004 gran 0x02 io
PCI: 00:17.0 18 <- [0x00000020c8 - 0x00000020cf] size 0x00000008 gran 0x03 io
PCI: 00:17.0 1c <- [0x00000020e4 - 0x00000020e7] size 0x00000004 gran 0x02 io
PCI: 00:17.0 20 <- [0x0000002080 - 0x000000209f] size 0x00000020 gran 0x05 io
PCI: 00:17.0 24 <- [0x00dfff4000 - 0x00dfff47ff] size 0x00000800 gran 0x0b mem
PCI: 00:18.0 10 <- [0x00000020d0 - 0x00000020d7] size 0x00000008 gran 0x03 io
PCI: 00:18.0 14 <- [0x00000020e8 - 0x00000020eb] size 0x00000004 gran 0x02 io
PCI: 00:18.0 18 <- [0x00000020d8 - 0x00000020df] size 0x00000008 gran 0x03 io
PCI: 00:18.0 1c <- [0x00000020ec - 0x00000020ef] size 0x00000004 gran 0x02 io
PCI: 00:18.0 20 <- [0x00000020a0 - 0x00000020bf] size 0x00000020 gran 0x05 io
PCI: 00:18.0 24 <- [0x00dfff4800 - 0x00dfff4fff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x00dfff5800 - 0x00dfff581f] size 0x00000020 gran 0x05 mem
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 1000 size 10f0 align 12 gran 0 limit ef9f flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base dfe00000 size 1f5820 align 20 gran 0 limit dfffffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
  PCI_DOMAIN: 0000 resource base 100000 size 7fd00000 align 0 gran 0 limit 0 flags e0004200 index 4
  PCI_DOMAIN: 0000 resource base 7fe00000 size 200000 align 0 gran 0 limit 0 flags f0000200 index 6
  PCI_DOMAIN: 0000 resource base 100000000 size 80000000 align 0 gran 0 limit 0 flags e0004200 index 7
  PCI_DOMAIN: 0000 resource base e0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 8
  PCI_DOMAIN: 0000 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0200200 index 9
   PCI: 00:00.0
   PCI: 00:00.0 resource base e0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
   PCI: 00:01.0
   PCI: 00:01.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c
   PCI: 00:01.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
   PCI: 00:01.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20
   PCI: 00:01.0 resource base dff00000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 10
   PCI: 00:02.0
   PCI: 00:03.0 child on link 0 PCI: 02:00.0
   PCI: 00:03.0 resource base 1000 size 1000 align 12 gran 12 limit ef9f flags 60080102 index 1c
   PCI: 00:03.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
   PCI: 00:03.0 resource base dfe00000 size 100000 align 20 gran 20 limit dfffffff flags 60080202 index 20
   PCI: 00:03.0 resource base dff20000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 10
    PCI: 02:00.0
    PCI: 02:00.0 resource base dfe00000 size 20000 align 17 gran 17 limit dfffffff flags 60000200 index 10
    PCI: 02:00.0 resource base 1000 size 20 align 5 gran 5 limit ef9f flags 60000100 index 18
    PCI: 02:00.0 resource base dfe20000 size 4000 align 14 gran 14 limit dfffffff flags 60000200 index 1c
   PCI: 00:04.0
   PCI: 00:0b.0
   PCI: 00:0b.0 resource base dff40000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 18
   PCI: 00:0b.0 resource base dffe0000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 20
   PCI: 00:0e.0
   PCI: 00:0f.0
   PCI: 00:11.0
   PCI: 00:13.0
   PCI: 00:13.0 resource base dfff5000 size 400 align 10 gran 10 limit dfffffff flags 60000201 index 10
   PCI: 00:14.0
   PCI: 00:14.0 resource base dff60000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 10
   PCI: 00:14.0 resource base 2000 size 20 align 5 gran 5 limit ef9f flags 60000100 index 18
   PCI: 00:14.0 resource base dffe4000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 20
   PCI: 00:14.1
   PCI: 00:14.1 resource base dff80000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 10
   PCI: 00:14.1 resource base 2020 size 20 align 5 gran 5 limit ef9f flags 60000100 index 18
   PCI: 00:14.1 resource base dffe8000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 20
   PCI: 00:14.2
   PCI: 00:14.2 resource base dffa0000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 10
   PCI: 00:14.2 resource base 2040 size 20 align 5 gran 5 limit ef9f flags 60000100 index 18
   PCI: 00:14.2 resource base dffec000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 20
   PCI: 00:14.3
   PCI: 00:14.3 resource base dffc0000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 10
   PCI: 00:14.3 resource base 2060 size 20 align 5 gran 5 limit ef9f flags 60000100 index 18
   PCI: 00:14.3 resource base dfff0000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 20
   PCI: 00:15.0
   PCI: 00:16.0
   PCI: 00:16.0 resource base dfff5400 size 400 align 10 gran 10 limit dfffffff flags 60000200 index 10
   PCI: 00:17.0
   PCI: 00:17.0 resource base 20c0 size 8 align 3 gran 3 limit ef9f flags 60000100 index 10
   PCI: 00:17.0 resource base 20e0 size 4 align 2 gran 2 limit ef9f flags 60000100 index 14
   PCI: 00:17.0 resource base 20c8 size 8 align 3 gran 3 limit ef9f flags 60000100 index 18
   PCI: 00:17.0 resource base 20e4 size 4 align 2 gran 2 limit ef9f flags 60000100 index 1c
   PCI: 00:17.0 resource base 2080 size 20 align 5 gran 5 limit ef9f flags 60000100 index 20
   PCI: 00:17.0 resource base dfff4000 size 800 align 11 gran 11 limit dfffffff flags 60000200 index 24
   PCI: 00:18.0
   PCI: 00:18.0 resource base 20d0 size 8 align 3 gran 3 limit ef9f flags 60000100 index 10
   PCI: 00:18.0 resource base 20e8 size 4 align 2 gran 2 limit ef9f flags 60000100 index 14
   PCI: 00:18.0 resource base 20d8 size 8 align 3 gran 3 limit ef9f flags 60000100 index 18
   PCI: 00:18.0 resource base 20ec size 4 align 2 gran 2 limit ef9f flags 60000100 index 1c
   PCI: 00:18.0 resource base 20a0 size 20 align 5 gran 5 limit ef9f flags 60000100 index 20
   PCI: 00:18.0 resource base dfff4800 size 800 align 11 gran 11 limit dfffffff flags 60000200 index 24
   PCI: 00:1f.0
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index d9
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index da
   PCI: 00:1f.0 resource base fee00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index db
   PCI: 00:1f.0 resource base fed1c000 size 4000 align 14 gran 14 limit 0 flags f0000200 index dc
   PCI: 00:1f.3
   PCI: 00:1f.3 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
   PCI: 00:1f.3 resource base dfff5800 size 20 align 5 gran 5 limit dfffffff flags 60000200 index 10
Done allocating resources.
Enabling resources...
PCI: 00:00.0 subsystem <- 0000/0000
PCI: 00:00.0 cmd <- 07
PCI: 00:01.0 bridge ctrl <- 0003
PCI: 00:01.0 cmd <- 02
PCI: 00:03.0 bridge ctrl <- 0003
PCI: 00:03.0 cmd <- 07
PCI: 00:0b.0 cmd <- 02
PCI: 00:0e.0 cmd <- 00
PCI: 00:0f.0 cmd <- 04
PCI: 00:13.0 subsystem <- 0000/0000
PCI: 00:13.0 cmd <- 06
PCI: 00:14.0 cmd <- 07
PCI: 00:14.1 cmd <- 03
PCI: 00:14.2 cmd <- 03
PCI: 00:14.3 cmd <- 03
PCI: 00:16.0 subsystem <- 0000/0000
PCI: 00:16.0 cmd <- 02
PCI: 00:17.0 subsystem <- 0000/0000
PCI: 00:17.0 cmd <- 03
PCI: 00:18.0 subsystem <- 0000/0000
PCI: 00:18.0 cmd <- 03
PCI: 00:1f.0 subsystem <- 0000/0000
PCI: 00:1f.0 cmd <- 07
PCI: 00:1f.3 subsystem <- 0000/0000
PCI: 00:1f.3 cmd <- 03
PCI: 02:00.0 cmd <- 03
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x00001000, code_size=0x00000031
Initializing CPU #0
CPU: vendor Intel device 406d8
CPU: family 06, model 4d, stepping 08
Enabling cache
CBFS: Looking for 'cpu_microcode_blob.bin'
CBFS: found.
microcode: sig=0x406d8 pf=0x1 revision=0x112
microcode: updated to revision 0x11d date=2013-10-29
CPU: Intel(R) Atom(TM) CPU  C2558  @ 2.40GHz.

Setting fixed MTRRs(0-88) Type: UC
Setting fixed MTRRs(0-16) Type: WB
DONE fixed MTRRs
call enable_fixed_mtrr()
CPU physical address size: 36 bits
Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
Setting variable MTRR 1, base: 4096MB, range: 2048MB, type WB
Setting variable MTRR 2, base: 2046MB, range:    2MB, type UC
Setting variable MTRR 3, base: 2048MB, range: 2048MB, type UC
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x00 done.
CPU: 0 has 4 cores 1 threads
CPU: 0 has core 2
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 2.
After apic_write.
Initializing CPU #1
Startup point 1.
Waiting for send to finish...
+CPU: vendor Intel device 406d8
Sending STARTUP #2 to 2.
After apic_write.
CPU: family 06, model 4d, stepping 08
Startup point 1.
Waiting for send to finish...
+Enabling cache
After Startup.
CBFS: Looking for 'cpu_microcode_blob.bin'
CPU: 0 has core 4
Asserting INIT.
Waiting for send to finish...
+CBFS: found.
microcode: sig=0x406d8 pf=0x1 revision=0x11d
microcode: updated to revision 0x11d date=2013-10-29
CPU: Intel(R) Atom(TM) CPU  C2558  @ 2.40GHz.

Setting fixed MTRRs(0-88) Type: UC
Deasserting INIT.
Waiting for send to finish...
+Setting fixed MTRRs(0-16) Type: WB
#startup loops: 2.
Sending STARTUP #1 to 4.
DONE fixed MTRRs
call enable_fixed_mtrr()
After apic_write.
CPU physical address size: 36 bits
Startup point 1.
Waiting for send to finish...
+Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
Sending STARTUP #2 to 4.
Setting variable MTRR 1, base: 4096MB, range: 2048MB, type WB
After apic_write.
Setting variable MTRR 2, base: 2046MB, range:    2MB, type UC
Startup point 1.
Waiting for send to finish...
+Setting variable MTRR 3, base: 2048MB, range: 2048MB, type UC
After Startup.
DONE variable MTRRs
Clear out the extra MTRR's
CPU: 0 has core 6
call enable_var_mtrr()
Asserting INIT.
Waiting for send to finish...
+Leave x86_setup_var_mtrrs
Initializing CPU #2

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

CPU: vendor Intel device 406d8
Setting up local apic...CPU: family 06, model 4d, stepping 08
 apic_id: 0x02 done.
Deasserting INIT.
Waiting for send to finish...
+CPU #1 initialized
#startup loops: 2.
Sending STARTUP #1 to 6.
After apic_write.
Enabling cache
Startup point 1.
Waiting for send to finish...
+CBFS: Looking for 'cpu_microcode_blob.bin'
Sending STARTUP #2 to 6.
CBFS: found.
After apic_write.
microcode: sig=0x406d8 pf=0x1 revision=0x112
Startup point 1.
Waiting for send to finish...
+microcode: updated to revision 0x11d date=2013-10-29
After Startup.
CPU #0 initialized
CPU: Intel(R) Atom(TM) CPU  C2558  @ 2.40GHz.
Waiting for 2 CPUS to stop

Setting fixed MTRRs(0-88) Type: UC
Initializing CPU #3
Setting fixed MTRRs(0-16) Type: WB
CPU: vendor Intel device 406d8
DONE fixed MTRRs
call enable_fixed_mtrr()
CPU: family 06, model 4d, stepping 08
CPU physical address size: 36 bits
Enabling cache
Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
CBFS: Looking for 'cpu_microcode_blob.bin'
Setting variable MTRR 1, base: 4096MB, range: 2048MB, type WB
CBFS: found.
Setting variable MTRR 2, base: 2046MB, range:    2MB, type UC
microcode: sig=0x406d8 pf=0x1 revision=0x11d
Setting variable MTRR 3, base: 2048MB, range: 2048MB, type UC
microcode: updated to revision 0x11d date=2013-10-29
DONE variable MTRRs
Clear out the extra MTRR's
CPU: Intel(R) Atom(TM) CPU  C2558  @ 2.40GHz.

Setting fixed MTRRs(0-88) Type: UC
call enable_var_mtrr()
Setting fixed MTRRs(0-16) Type: WB
Leave x86_setup_var_mtrrs
DONE fixed MTRRs
call enable_fixed_mtrr()

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

CPU physical address size: 36 bits
Setting up local apic...Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
 apic_id: 0x04 done.
Setting variable MTRR 1, base: 4096MB, range: 2048MB, type WB
CPU #2 initialized
Setting variable MTRR 2, base: 2046MB, range:    2MB, type UC
Waiting for 1 CPUS to stop
Setting variable MTRR 3, base: 2048MB, range: 2048MB, type UC
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x06 done.
CPU #3 initialized
All AP CPUs stopped (7398 loops)
PCI: 00:01.0 init
PCI: 00:03.0 init
PCI: 00:0b.0 init
PCI: 00:0e.0 init
PCI: 00:0f.0 init
PCI: 00:13.0 init
PCI: 00:14.0 init
PCI: 00:14.1 init
PCI: 00:14.2 init
PCI: 00:14.3 init
PCI: 00:16.0 init
EHCI: Setting up controller.. done.
PCI: 00:17.0 init
SATA: Initializing...
SATA: Controller in AHCI mode.
ABAR: DFFF4000
PCI: 00:18.0 init
SATA3: Initializing...
SATA3: Controller in AHCI mode.
ABAR: DFFF4800
PCI: 00:1f.0 init
Rangeley: lpc_init
PCI: 00:1f.3 init
PCI: 02:00.0 init
Devices initialized
Show all devs...After init.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 0
PCI: 00:03.0: enabled 1
PCI: 00:04.0: enabled 0
PCI: 00:11.0: enabled 0
PCI: 00:15.0: enabled 0
PCI: 00:13.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:17.0: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.3: enabled 1
PCI: 00:0b.0: enabled 1
PCI: 00:0e.0: enabled 1
PCI: 00:0f.0: enabled 1
PCI: 00:14.0: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PCI: 02:00.0: enabled 1
APIC: 02: enabled 1
APIC: 04: enabled 1
APIC: 06: enabled 1
Re-Initializing CBMEM area to 0x7fde0000
Adding CBMEM entry as no. 2
Moving GDT to 7fde2600...ok
Updating MRC cache data.
picked entry 2 from cache block
SF: Detected W25Q64 with page size 1000, total 800000
picked entry 3 from cache block when looking for empty block
We need to erase the MRC cache region
SF: erase 20 77  0  0 (771000)
SF: erase 20 77 10  0 (772000)
SF: erase 20 77 20  0 (773000)
SF: erase 20 77 30  0 (774000)
SF: erase 20 77 40  0 (775000)
SF: erase 20 77 50  0 (776000)
SF: erase 20 77 60  0 (777000)
SF: erase 20 77 70  0 (778000)
SF: Successfully erased 32768 bytes @ 0x770000
Finally: write MRC cache update to flash
SF: Winbond: Successfully programmed 8848 bytes @ 0x770000
High Tables Base is 7fde0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 3
Copying Interrupt Routing Table to 0x7fde2800... done.
PIRQ table: 320 bytes.
Wrote the mp table end at: 000f0410 - 000f059c
Adding CBMEM entry as no. 4
Wrote the mp table end at: 7fde3810 - 7fde399c
MP table: 412 bytes.
Adding CBMEM entry as no. 5
smbios_write_tables: 7fde4800
Root Device (Intel Mohon Peak platform)
APIC_CLUSTER: 0 (Intel Rangeley Northbridge)
APIC: 00 (Socket rPGA989 CPU)
PCI_DOMAIN: 0000 (Intel Rangeley Northbridge)
PCI: 00:00.0 (Intel Rangeley Northbridge)
PCI: 00:01.0 (Intel Rangeley Northbridge)
PCI: 00:02.0 (Intel Rangeley Northbridge)
PCI: 00:03.0 (Intel Rangeley Northbridge)
PCI: 00:04.0 (Intel Rangeley Northbridge)
PCI: 00:11.0 (Intel Rangeley Southbridge)
PCI: 00:15.0 (Intel Rangeley Southbridge)
PCI: 00:13.0 (Intel Rangeley Southbridge)
PCI: 00:16.0 (Intel Rangeley Southbridge)
PCI: 00:17.0 (Intel Rangeley Southbridge)
PCI: 00:18.0 (Intel Rangeley Southbridge)
PCI: 00:1f.0 (Intel Rangeley Southbridge)
PCI: 00:1f.3 (Intel Rangeley Southbridge)
PCI: 00:0b.0 ()
PCI: 00:0e.0 ()
PCI: 00:0f.0 ()
PCI: 00:14.0 ()
PCI: 00:14.1 ()
PCI: 00:14.2 ()
PCI: 00:14.3 ()
PCI: 02:00.0 ()
APIC: 02 ()
APIC: 04 ()
APIC: 06 ()
SMBIOS tables: 295 bytes.
Adding CBMEM entry as no. 6
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 3000
New low_table_end: 0x00000528
Now going to write high coreboot table at 0x7fde5000
rom_table_end = 0x7fde5000
Adjust low_table_end from 0x00000528 to 0x00001000 
Adjust rom_table_end from 0x7fde5000 to 0x7fdf0000 
Adding high table area
coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000a0000-00000000000fffff: RESERVED
 3. 0000000000100000-000000007fddffff: RAM
 4. 000000007fde0000-000000007fdfffff: CONFIGURATION TABLES
 5. 000000007fe00000-000000007fffffff: RESERVED
 6. 00000000e0000000-00000000e3ffffff: RESERVED
 7. 00000000fec00000-00000000fec00fff: RESERVED
 8. 00000000fed1c000-00000000fed1ffff: RESERVED
 9. 00000000fee00000-00000000fee00fff: RESERVED
10. 00000000ff800000-00000000ffffffff: RESERVED
11. 0000000100000000-000000017fffffff: RAM
Wrote coreboot table at: 7fde5000, 0x23c bytes, checksum 9457
coreboot table: 596 bytes.
Multiboot Information structure has been written.
 0. FREE SPACE 7fded000 00013000
 1. MRC DATA   7fde0200 00002400
 2. GDT        7fde2600 00000200
 3. IRQ TABLE  7fde2800 00001000
 4. SMP TABLE  7fde3800 00001000
 5. SMBIOS     7fde4800 00000800
 6. COREBOOT   7fde5000 00008000
CBFS: Looking for 'fallback/payload'
CBFS: found.
Got a payload
CPU0: stack from 00198000 to 001a0000:Lowest stack address 0019fb28
Loading segment from rom address 0xffc6caf8
  code (compression=1)
  New segment dstaddr 0xe4350 memsize 0x1bcb0 srcaddr 0xffc6cb30 filesize 0xe50c
  (cleaned up) New segment addr 0xe4350 size 0x1bcb0 offset 0xffc6cb30 filesize 0xe50c
Loading segment from rom address 0xffc6cb14
  Entry Point 0x00000000
Payload (probably SeaBIOS) loaded into a reserved area in the lower 1MB
Loading Segment: addr: 0x00000000000e4350 memsz: 0x000000000001bcb0 filesz: 0x000000000000e50c
lb: [0x0000000000100000, 0x00000000001a4000)
Post relocation: addr: 0x00000000000e4350 memsz: 0x000000000001bcb0 filesz: 0x000000000000e50c
using LZMA
[ 0x000e4350, 00100000, 0x00100000) <- ffc6cb30
dest 000e4350, end 00100000, bouncebuffer 7fc98000
Loaded segments
Jumping to boot code at fd567
entry    = 0x000fd567
lb_start = 0x00100000
lb_size  = 0x000a4000
adjust   = 0x7fc3c000
buffer   = 0x7fc98000
     elf_boot_notes = 0x001185b4
adjusted_boot_notes = 0x7fd545b4
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Linux version 3.3.4-5.fc17.x86_64 (mockbuild@x86-14.phx2.fedoraproject.org) (gcc version 4.7.0 20120504 (Red Hat 4.7.0-4) (GCC) ) #1 SMP Mon May 7 17:29:34 UTC 2012
[    0.000000] Command line: BOOT_IMAGE=/vmlinuz-3.3.4-5.fc17.x86_64 root=UUID=c4d4a429-d880-4caa-831e-9e95b5595f67 ro rd.md=0 rd.lvm=0 rd.dm=0 SYSFONT=True KEYTABLE=us rd.luks=0 LANG=en_US.UTF-8 console=ttyS1,115200n8
[    0.000000] BIOS-provided physical RAM map:
[    0.000000]  BIOS-e820: 0000000000000000 - 000000000009f800 (usable)
[    0.000000]  BIOS-e820: 000000000009f800 - 00000000000a0000 (reserved)
[    0.000000]  BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
[    0.000000]  BIOS-e820: 0000000000100000 - 000000007fdde000 (usable)
[    0.000000]  BIOS-e820: 000000007fdde000 - 0000000080000000 (reserved)
[    0.000000]  BIOS-e820: 00000000e0000000 - 00000000e4000000 (reserved)
[    0.000000]  BIOS-e820: 00000000fec00000 - 00000000fec01000 (reserved)
[    0.000000]  BIOS-e820: 00000000fed1c000 - 00000000fed20000 (reserved)
[    0.000000]  BIOS-e820: 00000000fee00000 - 00000000fee01000 (reserved)
[    0.000000]  BIOS-e820: 00000000ff800000 - 0000000100000000 (reserved)
[    0.000000]  BIOS-e820: 0000000100000000 - 0000000180000000 (usable)
[    0.000000] NX (Execute Disable) protection: active