<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote"><div>Post code 0x0000 could also be the case the you do not have the latest microcode patches. Please double check.</div><div><br></div><div>Jiming</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Message: 1<br>
Date: Sun, 2 Nov 2014 18:31:59 +0530<br>
From: Gailu Singh <<a href="mailto:gailu96@gmail.com">gailu96@gmail.com</a>><br>
To: Sean McNeil <<a href="mailto:seanmcneil3@gmail.com">seanmcneil3@gmail.com</a>><br>
Cc: coreboot <<a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a>><br>
Subject: Re: [coreboot] Coreboot with Intel FSP on BayleyBay Help<br>
Message-ID:<br>
<<a href="mailto:CAOifn%2B2aM5FE6J_Vs0a_t%2B9YOdi1ZSZvhtSW6Jf04HUnQhPmBA@mail.gmail.com">CAOifn+2aM5FE6J_Vs0a_t+9YOdi1ZSZvhtSW6Jf04HUnQhPmBA@mail.gmail.com</a>><br>
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<br>
Hi Sean,<br>
<br>
1. This is not for a real project and we are trying to understand FSP<br>
interaction with coreboot to look at feasibility for considering coreboot<br>
in our future projects. Unfortunately I do not have board documentation so<br>
was not able to determine which one is serial port 0 though I know that<br>
port 0 is specified in coreboot config. That was the reason I was trying on<br>
all 3 available ports.<br>
2. I am not using .fd directly. I believe that FSP need to be included in<br>
bootloader (coreboot in this case) and we are providing path to coreboot so<br>
that it can be included in coreboot. In my original post I only said that I<br>
copied .fd to a path expected by coreboot configuration. May I know how<br>
did you conclude that I am using it directly? May be that can give me some<br>
pointer.<br>
3. I had checked the bsf file in the FSP kit with BCT tool and it is<br>
configured for non-ECC RAM, so I believe that no change is required in .fd.<br>
Am I wrong?<br>
4. Yes, I agree that there is no documentation available on how to create<br>
entire 8MB binary with Firmware Description, TXE, coreboot etc so for safe<br>
route I only touched upper 2 MB as recommended in one of the initial commit<br>
for baytrail FSP integration and some posts related to similar discussion.<br>
<br>
<br>
<br>
On Sun, Nov 2, 2014 at 3:49 PM, Sean McNeil <<a href="mailto:seanmcneil3@gmail.com">seanmcneil3@gmail.com</a>> wrote:<br>
<br>
> Coreboot and FSP are not as easy to understand as you can see. I also<br>
> would suggest that you seek assistance from either Sage (who has good<br>
> experience that I understand serves the USA and Europe markets and<br>
> contributed the current Coreboot+FSP code) or perhaps a company in Asia<br>
> such as Zien Solutions (of Vietnam). There are a number of issues that you<br>
> are failing to understand:<br>
><br>
> 1) As stated, the first serial port is actually connected to a USB->Serial<br>
> converter and delivered out of the microUSB connector on the CRB.<br>
> 2) You need to configure the FSP with Intels program to create a ROMable<br>
> image and not use the .fd file directly.<br>
> 3) BayleyBay needs to be configured for non-ECC RAM whereas Bakersport<br>
> needs to be configured for ECC.<br>
> 4) You don't necessarily need the TXE security module, but you could very<br>
> well cause problems if it is partially overwritten. Best is to create a<br>
> correct 8MB image to flash that has the proper Intel Firmware Description<br>
> block at the beginning.<br>
><br>
> Regards,<br>
> Sean<br>
><br>
><br>
> On 11/02/2014 02:25 AM, Gaumless via coreboot wrote:<br>
><br>
>> First, the serial ports: The serial console is on the first serial port<br>
>> on the micro-USB connection.<br>
>><br>
>> The 0x0000 on the post code display means that it's not actually starting<br>
>> to boot - it's probably hanging in the TXE. There are known issues with<br>
>> upgrading to coreboot from some of the bayleybay roms. I thought Intel was<br>
>> going to document that, but I don't know if they did.<br>
>><br>
>> The Gold 2 FSP doesn't support D0 parts, so if you have a D0, you need<br>
>> the Gold 3. Also, the FSP is targeted at the embedded sku Baytrail-I. It<br>
>> might work with M/D parts, I haven't tested that.<br>
>><br>
>> Assuming all that is ok, you probably need to start from a different<br>
>> rom. It might be failing because of the TXE security. You'll probably<br>
>> need to talk to your Intel contact to get that update.<br>
>><br>
>> Finally, if this is not a personal project, you might be interested in<br>
>> contacting Sage and look at purchasing a BSP to get up and running. Either<br>
>> way, let us know whether you make progress or need more help.<br>
>><br>
>> Martin<br>
>><br>
>><br>
>> On Nov 1, 2014, at 11:48 AM, Gailu Singh via coreboot <<br>
>>> <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a>> wrote:<br>
>>><br>
>>> Hi Experts,<br>
>>><br>
>>> I am trying to boot BayleyBay CRB Rev 3 using coreboot and have no<br>
>>> success so far. I have serial port (DB9) connected and using 115200 Baud<br>
>>> Rate. No message comes on serial at all. Here is the procedure I followed.<br>
>>><br>
>>> 1. Pulled latest coreboot from git.<br>
>>> 2. Pulled following from BAY_TRAIL_FSP_KIT. The reason for doing it is<br>
>>> that BAYTRAIL_FSP.fd is not in git and .config refers to it. Also .config<br>
>>> refers to ../intel/cpu/baytrail/microcode<br>
>>> a) created intel directory parallel to coreboot and copied<br>
>>> BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd in to<br>
>>> intel/fsp/baytrail/BAYTRAIL_FSP.fd<br>
>>> b) Copied *.h from Microcode folder in the kit to<br>
>>> intel/cpu/baytrail/microcode.<br>
>>> 3. Configured the coreboot for mainboard as intel bayleybay. My .config<br>
>>> is attached.<br>
>>> 4. Build Coreboot. Below is the prints from cbfstool.<br>
>>> cmos_layout.bin 0x0 cmos_layout 1132<br>
>>> fallback/romstage 0x4c0 stage 27813<br>
>>> fallback/ramstage 0x71c0 stage 67431<br>
>>> fallback/payload 0x17980 payload 268859<br>
>>> config 0x59400 raw 4363<br>
>>> (empty) 0x5a540 null 744088<br>
>>> cpu_microcode_blob.bin 0x110000 microcode 104448<br>
>>> (empty) 0x129840 null 157528<br>
>>> mrc.cache 0x14ffc0 (unknown) 65536<br>
>>> (empty) 0x160000 null 393112<br>
>>> fsp.bin 0x1bffc0 (unknown) 229376<br>
>>> (empty) 0x1f8000 null 31640<br>
>>> 5. Flashed the coreboot.rom in upper 2MB (0X0600000-0x07FFFFF)<br>
>>> 6. Reboot the board<br>
>>> 7. Nothing comes on Serial Console (DB9). Also tried to connect Micro<br>
>>> usb cable which detects two serial ports but no output to any of them as<br>
>>> well.<br>
>>> 8. Before flashing coreboot.rom, 4 digit display was displaying<br>
>>> something on two digits and rest two were zero. Now all 4 digits stays at<br>
>>> zeros.<br>
>>><br>
>>> Looking for help to get at least serial working so that I can get some<br>
>>> logs to debug it. I do not have copy of original BIOS that was there in<br>
>>> Flash and forgot to make a copy using programmer though I ensured that I<br>
>>> only touch upper 2MB. I am stuck and have no logs to debug it.<br>
>>><br>
>>> Thanks in advance.<br>
>>> <my.config><br>
>>> --<br>
>>> coreboot mailing list: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
>>> <a href="http://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">http://www.coreboot.org/mailman/listinfo/coreboot</a><br>
>>><br>
>><br>
><br>
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