<div dir="ltr"><div><div><div>Hi Werner,<br><br></div>Thanks for your help and support. It was indeed due to wrong FSP. D0 stepping is installed and it only worked now with Gold3 FSP and updated microcode.<br><br></div>Thank you very much.<br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Nov 4, 2014 at 12:48 AM, Werner Zeh <span dir="ltr"><<a href="mailto:werner.zeh@gmx.net" target="_blank">werner.zeh@gmx.net</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi.<br>
<br>
Now you have coreboot running.<br>
coreboot searches for FSP, finds it and executes the first call into it.<br>
FSP returns with an error and what you see is this (taken from src/drivers/intel/fsp/cache_<u></u>as_ram.inc):<br>
<br>
/*<br>
* Failures for postcode 0xBB - failed in the FSP:<br>
*<br>
* 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully.<br>
* 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.<br>
* 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.<br>
* 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.<br>
* 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed<br>
* 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked<br>
*/<br>
<br>
So what you actually see is error code 0x07 from FSP. This can mean that your CPU is not supported by this FSP version.<br>
If you use GOLD1 or GOLD2, then a D0 stepping is not supported and if you have in advance a D0 stepping installed on your board,<br>
than you have to use GOLD3 FSP release as it was already mentioned.<br>
<br>
I had the same issue and it was due to missing D0-Support in GOLD1 release. So, I would suggest to try the right FSP-release from Intel.<br>
<br>
Bye<br>
Werner<br>
<br>
Am 03.11.2014 um 17:23 schrieb Gailu Singh via coreboot:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">
With the changed TXE/descriptor, it moved ahead but now toggling between POST codes 0x66 and 0x07. I checked ./src/include/console/post_<u></u>codes.h and these POST codes are not defined there so I doubt that these are coming from coreboot code. Are these post codes coming from FSP code? If yes, How do I interpret them? Do I need to ask Intel? Any pointers please?<br>
<br></span><div><div class="h5">
On Sun, Nov 2, 2014 at 6:50 PM, Sean McNeil <<a href="mailto:seanmcneil3@gmail.com" target="_blank">seanmcneil3@gmail.com</a> <mailto:<a href="mailto:seanmcneil3@gmail.com" target="_blank">seanmcneil3@gmail.com</a>><u></u>> wrote:<br>
<br>
You mentioned just copying the .fd file, so I assumed it was being<br>
used directly in your coreboot image. FSP needs to be incorporated<br>
into flash, yes. It should, however, be patched with the BCT<br>
program as what is provided in the .fd is usually not patched with<br>
the a configuration that you desire. Thus you should run bct and<br>
configure/patch the .fd and generate a .bin to include into coreboot.<br>
<br>
I am a little confused by your email below. You state that you are<br>
not using the .fd directly then contradict yourself in the next<br>
sentence. Bottom line is I would not include any .fd file from the<br>
FSP archive directly. Use BCT to patch it and do not name it .fd.<br>
This avoids any confusion regarding whether you are including a<br>
patched FSP or not. Just because there is a bsf file included in<br>
the GOLD release doesn't mean that the .fd was patched with those<br>
settings and that it is valid.<br>
<br>
Best of luck to you. There are many issues you will have to<br>
resolve dealing with new hardware. I've gone through the process<br>
with a lot of support from Intel and it is not that easy.<br>
Especially when certain components found on the CRB are not<br>
provided on custom hardware.<br>
<br>
Cheers,<br>
Sean<br>
<br>
<br>
On 11/02/2014 08:01 PM, Gailu Singh wrote:<br>
</div></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div class="h5">
Hi Sean,<br>
<br>
1. This is not for a real project and we are trying to understand<br>
FSP interaction with coreboot to look at feasibility for<br>
considering coreboot in our future projects. Unfortunately I do<br>
not have board documentation so was not able to determine which<br>
one is serial port 0 though I know that port 0 is specified in<br>
coreboot config. That was the reason I was trying on all 3<br>
available ports.<br>
2. I am not using .fd directly. I believe that FSP need to be<br>
included in bootloader (coreboot in this case) and we are<br>
providing path to coreboot so that it can be included in<br>
coreboot. In my original post I only said that I copied .fd to a<br>
path expected by coreboot configuration. May I know how did you<br>
conclude that I am using it directly? May be that can give me<br>
some pointer.<br>
3. I had checked the bsf file in the FSP kit with BCT tool and it<br>
is configured for non-ECC RAM, so I believe that no change is<br>
required in .fd. Am I wrong?<br>
4. Yes, I agree that there is no documentation available on how<br>
to create entire 8MB binary with Firmware Description, TXE,<br>
coreboot etc so for safe route I only touched upper 2 MB as<br>
recommended in one of the initial commit for baytrail FSP<br>
integration and some posts related to similar discussion.<br>
<br>
<br>
<br>
On Sun, Nov 2, 2014 at 3:49 PM, Sean McNeil<br></div></div><div><div class="h5">
<<a href="mailto:seanmcneil3@gmail.com" target="_blank">seanmcneil3@gmail.com</a> <mailto:<a href="mailto:seanmcneil3@gmail.com" target="_blank">seanmcneil3@gmail.com</a>><u></u>> wrote:<br>
<br>
Coreboot and FSP are not as easy to understand as you can<br>
see. I also would suggest that you seek assistance from<br>
either Sage (who has good experience that I understand serves<br>
the USA and Europe markets and contributed the current<br>
Coreboot+FSP code) or perhaps a company in Asia such as Zien<br>
Solutions (of Vietnam). There are a number of issues that you<br>
are failing to understand:<br>
<br>
1) As stated, the first serial port is actually connected to<br>
a USB->Serial converter and delivered out of the microUSB<br>
connector on the CRB.<br>
2) You need to configure the FSP with Intels program to<br>
create a ROMable image and not use the .fd file directly.<br>
3) BayleyBay needs to be configured for non-ECC RAM whereas<br>
Bakersport needs to be configured for ECC.<br>
4) You don't necessarily need the TXE security module, but<br>
you could very well cause problems if it is partially<br>
overwritten. Best is to create a correct 8MB image to flash<br>
that has the proper Intel Firmware Description block at the<br>
beginning.<br>
<br>
Regards,<br>
Sean<br>
<br>
<br>
On 11/02/2014 02:25 AM, Gaumless via coreboot wrote:<br>
<br>
First, the serial ports: The serial console is on the<br>
first serial port on the micro-USB connection.<br>
<br>
The 0x0000 on the post code display means that it's not<br>
actually starting to boot - it's probably hanging in the<br>
TXE. There are known issues with upgrading to coreboot<br>
from some of the bayleybay roms. I thought Intel was<br>
going to document that, but I don't know if they did.<br>
<br>
The Gold 2 FSP doesn't support D0 parts, so if you have a<br>
D0, you need the Gold 3. Also, the FSP is targeted at<br>
the embedded sku Baytrail-I. It might work with M/D<br>
parts, I haven't tested that.<br>
<br>
Assuming all that is ok, you probably need to start from<br>
a different rom. It might be failing because of the TXE<br>
security. You'll probably need to talk to your Intel<br>
contact to get that update.<br>
<br>
Finally, if this is not a personal project, you might be<br>
interested in contacting Sage and look at purchasing a<br>
BSP to get up and running. Either way, let us know<br>
whether you make progress or need more help.<br>
<br>
Martin<br>
<br>
<br>
On Nov 1, 2014, at 11:48 AM, Gailu Singh via coreboot<br>
<<a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br></div></div><div><div class="h5">
<mailto:<a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a>><u></u>> wrote:<br>
<br>
Hi Experts,<br>
<br>
I am trying to boot BayleyBay CRB Rev 3 using<br>
coreboot and have no success so far. I have serial<br>
port (DB9) connected and using 115200 Baud Rate. No<br>
message comes on serial at all. Here is the procedure<br>
I followed.<br>
<br>
1. Pulled latest coreboot from git.<br>
2. Pulled following from BAY_TRAIL_FSP_KIT. The<br>
reason for doing it is that BAYTRAIL_FSP.fd is not<br>
in git and .config refers to it. Also .config refers<br>
to ../intel/cpu/baytrail/<u></u>microcode<br>
a) created intel directory parallel to coreboot<br>
and copied BAYTRAIL_FSP_GOLD_002_10-<u></u>JANUARY-2014.fd<br>
in to intel/fsp/baytrail/BAYTRAIL_<u></u>FSP.fd<br>
b) Copied *.h from Microcode folder in the kit<br>
to intel/cpu/baytrail/microcode.<br>
3. Configured the coreboot for mainboard as intel<br>
bayleybay. My .config is attached.<br>
4. Build Coreboot. Below is the prints from cbfstool.<br>
cmos_layout.bin 0x0 cmos_layout 1132<br>
fallback/romstage 0x4c0 stage 27813<br>
fallback/ramstage 0x71c0 stage 67431<br>
fallback/payload 0x17980 payload 268859<br>
config 0x59400 raw 4363<br>
(empty) 0x5a540 null 744088<br>
cpu_microcode_blob.bin 0x110000 microcode 104448<br>
(empty) 0x129840 null 157528<br>
mrc.cache 0x14ffc0 (unknown) 65536<br>
(empty) 0x160000 null 393112<br>
fsp.bin 0x1bffc0 (unknown) 229376<br>
(empty) 0x1f8000 null 31640<br>
5. Flashed the coreboot.rom in upper 2MB<br>
(0X0600000-0x07FFFFF)<br>
6. Reboot the board<br>
7. Nothing comes on Serial Console (DB9). Also tried<br>
to connect Micro usb cable which detects two serial<br>
ports but no output to any of them as well.<br>
8. Before flashing coreboot.rom, 4 digit display was<br>
displaying something on two digits and rest two were<br>
zero. Now all 4 digits stays at zeros.<br>
<br>
Looking for help to get at least serial working so<br>
that I can get some logs to debug it. I do not have<br>
copy of original BIOS that was there in Flash and<br>
forgot to make a copy using programmer though I<br>
ensured that I only touch upper 2MB. I am stuck and<br>
have no logs to debug it.<br>
<br>
Thanks in advance.<br>
<my.config><br>
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<br>
<br>
<br>
</blockquote>
<br>
<br>
<br>
<br>
</blockquote>
<br>
</blockquote></div><br></div>