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<div class="moz-cite-prefix">Hi,<br>
<br>
More information on this.<br>
<br>
The POST code sequence (as far I can see, but I'm not Steeve
Austin...) is:<br>
40h -> 47h -> A9h<br>
<br>
IMHO, we are parsing following code from
./src/southbridge/intel/fsp_rangeley/romstage.c<br>
<small><tt>void main(FSP_INFO_HEADER *fsp_info_header)</tt><tt><br>
</tt><tt>{</tt><tt><br>
</tt><tt> uint32_t fd_mask = 0;</tt><tt><br>
</tt><tt> uint32_t func_dis = DEFAULT_PBASE + PBASE_FUNC_DIS;</tt><tt><br>
</tt><tt><br>
</tt><tt> /*</tt><tt><br>
</tt><tt> * Do not use the Serial Console before it is
setup.</tt><tt><br>
</tt><tt> * This causes the I/O to clog and a side effect is</tt><tt><br>
</tt><tt> * that the reset button stops functioning. So</tt><tt><br>
</tt><tt> * instead just use outb so it doesn't output to
the</tt><tt><br>
</tt><tt> * console when CONFIG_CONSOLE_POST.</tt><tt><br>
</tt><tt> */</tt><tt><br>
</tt><tt> outb(0x40, 0x80);</tt><tt><br>
</tt><tt><br>
</tt><tt> /* Rangeley UART POR state is enabled */</tt><tt><br>
</tt><tt> console_init();</tt><tt><br>
</tt><tt> post_code(0x41);</tt><tt><br>
</tt><tt><br>
</tt><tt> /* Enable GPIOs BAR */</tt><tt><br>
</tt><tt> pci_write_config32(SOC_LPC_DEV, GBASE,
DEFAULT_GPIOBASE|0x02);</tt><tt><br>
</tt><tt><br>
</tt><tt> early_mainboard_romstage_entry();</tt><tt><br>
</tt><tt><br>
</tt><tt> post_code(0x42);</tt><tt><br>
</tt><tt> rangeley_sb_early_initialization();</tt><tt><br>
</tt><tt><br>
</tt><tt> post_code(0x46);</tt><tt><br>
</tt><tt> /* Program any required function disables */</tt><tt><br>
</tt><tt> get_func_disables(&fd_mask);</tt><tt><br>
</tt><tt><br>
</tt><tt> if (fd_mask != 0) {</tt><tt><br>
</tt><tt> write32(func_dis, read32(func_dis) | fd_mask);</tt><tt><br>
</tt><tt> /* Ensure posted write hits. */</tt><tt><br>
</tt><tt> read32(func_dis);</tt><tt><br>
</tt><tt> }</tt><tt><br>
</tt><tt><br>
</tt><tt> /*</tt><tt><br>
</tt><tt> * Call early init to initialize memory and chipset.
This function returns</tt><tt><br>
</tt><tt> * to the romstage_main_continue function with a
pointer to the HOB</tt><tt><br>
</tt><tt> * structure.</tt><tt><br>
</tt><tt> */</tt><tt><br>
</tt><tt> post_code(0x47);</tt><tt><br>
</tt><tt> printk(BIOS_DEBUG, "Starting the Intel FSP
(early_init)\n");</tt><tt><br>
</tt><tt> fsp_early_init(fsp_info_header);</tt><tt><br>
</tt><tt> die("Uh Oh! fsp_early_init should not return
here.\n");</tt><tt><br>
</tt><tt>}</tt><tt><br>
</tt></small><br>
... and I'm affraid we get stucked in the fsp_early_init()
function ... :-(<br>
<br>
Regards.<br>
Patrick Agrain<br>
<br>
Le 11/03/2015 16:21, Patrick Agrain a écrit :<br>
</div>
<blockquote cite="mid:55005D6F.2010000@alcatel-lucent.com"
type="cite">
<meta http-equiv="Content-Type" content="text/html;
charset=ISO-8859-1">
Hello Kyösti,<br>
<br>
I tried what you suggested below:<br>
<br>
- Enabled EARLY_PCI_BRIDGE<br>
- Set Bridge at D:1 F:0<br>
- Enabled OXI PCIe952 and disabled SERIAL_PORT_ON_SUPERIO.<br>
Reboot Mohon Peak CRB: failed. No output. POST code at 0xA9.<br>
<br>
Will try to get further. <br>
If anybody has an idea...<br>
<br>
Regards,<br>
Patrick Agrain<br>
<br>
<pre>On Fri, 2015-03-06 at 17:25 +0100, Patrick Agrain wrote:
><i> Hello everybody,
</i>><i>
</i>><i> Do you think that it would be possible to output the console messages
</i>><i> from coreboot (seabios) on another UART port (strapped to be visible on
</i>><i> Memory-based space or IO Space) connected on a PCIe slot ?
</i>><i>
</i>
Yes, it has been done before.
I should have a hack for SeaBIOS to support memory-mapped UART
somewhere, I will go and look. If I remember correctly SeaBIOS boot
media selection only works from local keyboard, not over serial.
><i> I've purchased a StarTech UART board with an OXPCIe952 chip, with the
</i>><i> same IDs as visible in ./src/drivers/uart/oxpcie.c.
</i>><i>
</i>><i> On
</i>><i> <a moz-do-not-send="true" href="http://www.coreboot.org/Serial_console#PCIe.2FMini_PCIe_based_serial_cards,">http://www.coreboot.org/Serial_console#PCIe.2FMini_PCIe_based_serial_cards,</a>
</i>><i> what is behind the sentence:
</i>><i> "In order to use the card for romstage debugging, minimal setup of the
</i>><i> PCIe bridge and the MPEX2S952 have to be added to romstage.c" ?
</i>><i>
</i>
You need to enable OxPCIe support and set EARLY_PCI_BRIDGE_* variables
in menuconfig. If you can boot to OS with that plaform, with the serial
card installed, get the location of PCIe rootport (aka. parent bridge)
for OxPCIe card with lspci -vv command.
Once you have OS shell, both coreboot and SeaBIOS console messages are
available from CBMEM console using 'cbmem -c' command.
><i> Thanks in advance.
</i>><i> Best regards,
</i>><i> Patrick Agrain
</i>><i>
</i>
HTH,
Kyösti</pre>
<br>
</blockquote>
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