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<div class="moz-cite-prefix">Hello,<br>
<br>
One step further !!<br>
<br>
I succeed to get it working.<br>
<br>
Several modification has to be made. I will try (next week) to get
them in a "readable form".<br>
- in ./src/device/pci_early.c:pci_early_bridge_init() : <br>
-- secondary = 1 for Mohon Peak.<br>
-- remove udelay() in PCI_VENDOR_ID reading (that's the big
point). I will try to have a look at it. Probably something very
specific to this chipset.<br>
-- Put 'if (ret)' condition on the last
'pci_bridge_set_secondary(p2p_bridge, 0);'.<br>
- in ./src/drivers/uart/oxpcie_early.c:pci_early_device_probe() :<br>
-- uart1base is at CONFIG_EARLY_PCI_MMIO_BASE + 0x1200 for the
Startech board I have.<br>
<br>
BTW, I also included the patch covered by <a
href="http://review.coreboot.org/#/c/8660/">http://review.coreboot.org/#/c/8660/</a>.
Compiler does not complain anymore (and 'in fine' it works).<br>
<br>
Logs are now available from 'coreboot-<...> ramstage
starting'.<br>
<br>
Thanks for your support.<br>
Regards,<br>
Patrick Agrain<br>
<br>
Le 12/03/2015 10:02, Patrick Agrain a écrit :<br>
</div>
<blockquote cite="mid:55015623.3030008@alcatel-lucent.com"
type="cite">
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<pre>Hello,
More on this topic.
Kyösti, as required, here are the info.
- I'm able to boot a Linux OS with (internal) uart1 from Atom.
- I'm also to boot the Linux with following command-line : kernel /boot/vmlinuz-2.6.32-xx-dhs3 root=/dev/sda2
console=uart8250,mmio,0xdf601000,115200n8 panic=5. The kernel logs are then sent to the external UART,
as soon as the serial driver is loaded.. So far so good...
Here are the lspci information from a Mohon Peak.
[root@mohon_peak ~]# lspci -t
-[0000:00]-+-00.0
+-01.0-[01]----00.0
+-03.0-[02-06]----00.0-[03-06]--+-04.0-[04]--
| +-05.0-[05]--+-00.0
| | \-00.1
| \-08.0-[06]--
+-0e.0
+-0f.0
+-13.0
+-14.0
+-14.1
+-16.0
+-17.0
+-18.0
+-1f.0
\-1f.3
[root@mohon_peak ~]#
[root@mohon_peak ~]# lspci -vv -d 1415:c158
01:00.0 Serial controller: Oxford Semiconductor Ltd OXPCIe952 Dual 16C950 UART (prog-if 02 [16550])
Subsystem: Oxford Semiconductor Ltd OXPCIe952 Dual 16C950 UART
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ 16
Region 0: Memory at df600000 (32-bit, non-prefetchable) [size=16K]
Region 1: Memory at df200000 (32-bit, non-prefetchable) [size=2M]
Region 2: Memory at df400000 (32-bit, non-prefetchable) [size=2M]
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=55mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [70] Express (v1) Endpoint, MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <128ns, L1 <2us
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 unlimited, L1 unlimited
ClockPM+ Surprise- LLActRep- BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
Capabilities: [b0] MSI-X: Enable- Count=16 Masked-
Vector table: BAR=1 offset=001b3000
PBA: BAR=1 offset=001b2000
Capabilities: [100 v1] Device Serial Number 00-30-e0-11-11-00-01-50
Capabilities: [110 v1] Power Budgeting <?>
Kernel driver in use: serial
[root@mohon_peak ~]#
[root@mohon_peak ~]# dmesg | grep tty
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
ttyS2: detected caps 00000700 should be 00000100
0000:01:00.0: ttyS2 at MMIO 0xdf601000 (irq = 16) is a 16C950/954
ttyS3: detected caps 00000700 should be 00000100
0000:01:00.0: ttyS3 at MMIO 0xdf601200 (irq = 16) is a 16C950/954
[root@mohon_peak ~]#
Kyösti, I agree with you concerning the A9h post code. IMHO, I think it is issued by the Intel FSP.
BTW,
compiler complains about a mismatch argument type on read8() and write8() in ./src/drivers/uart/uart8250mem.c
----
src/drivers/uart/uart8250mem.c: In function 'uart8250_read':
src/drivers/uart/uart8250mem.c:39:2: error: passing argument 1 of 'read8' makes pointer from integer without a cast [-Werror]
return read8((uintptr_t) (base + reg));
^
In file included from src/drivers/uart/uart8250mem.c:21:0:
src/arch/x86/include/arch/io.h:145:54: note: expected 'const volatile void *' but argument is of type 'unsigned int'
static inline __attribute__((always_inline)) uint8_t read8(const volatile void *addr)
^
src/drivers/uart/uart8250mem.c: In function 'uart8250_write':
src/drivers/uart/uart8250mem.c:45:2: error: passing argument 1 of 'write8' makes pointer from integer without a cast [-Werror]
write8((uintptr_t) (base + reg), data);
^
In file included from src/drivers/uart/uart8250mem.c:21:0:
src/arch/x86/include/arch/io.h:160:51: note: expected 'volatile void *' but argument is of type 'unsigned int'
static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value)
^
cc1: all warnings being treated as errors
make: *** [build/drivers/uart/uart8250mem.romstage.o] Error 1
----
Hope it helps.
Best regards,
Patrick
On Wed, 2015-03-11 at 16:21 +0100, Patrick Agrain wrote:
><i> Hello Kyösti,
</i>><i>
</i>><i> I tried what you suggested below:
</i>><i>
</i>><i> - Enabled EARLY_PCI_BRIDGE
</i>><i> - Set Bridge at D:1 F:0
</i>><i> - Enabled OXI PCIe952 and disabled SERIAL_PORT_ON_SUPERIO.
</i>><i> Reboot Mohon Peak CRB: failed. No output. POST code at 0xA9.
</i>><i>
</i>
You also need to set EARLY_PCI_MMIO_BASE. If you cannot boot this board
to OS yet and run lspci command, try with 0xfef00000 that should be
safely out of the way of other resources.
I don't think post 0xA9 originates from coreboot proper.
><i> Will try to get further.
</i>><i> If anybody has an idea...
</i>
If by any means possible, boot your Mohon Peak board to OS, check your
serial terminal parameters and cables, and prepare the OS for logins
over serial line. Then return here with the lspci -vv output so we have
something to work with.
Kyösti
</pre>
<br>
<br>
Le 11/03/2015 17:44, Patrick Agrain a écrit :<br>
</div>
<blockquote cite="mid:550070EE.7010602@alcatel-lucent.com"
type="cite">
<div class="moz-cite-prefix">Hi,<br>
<br>
More information on this.<br>
<br>
The POST code sequence (as far I can see, but I'm not Steeve
Austin...) is:<br>
40h -> 47h -> A9h<br>
<br>
IMHO, we are parsing following code from
./src/southbridge/intel/fsp_rangeley/romstage.c<br>
<small><tt>void main(FSP_INFO_HEADER *fsp_info_header)</tt><tt><br>
</tt><tt>{</tt><tt><br>
</tt><tt> uint32_t fd_mask = 0;</tt><tt><br>
</tt><tt> uint32_t func_dis = DEFAULT_PBASE +
PBASE_FUNC_DIS;</tt><tt><br>
</tt><tt><br>
</tt><tt> /*</tt><tt><br>
</tt><tt> * Do not use the Serial Console before it is
setup.</tt><tt><br>
</tt><tt> * This causes the I/O to clog and a side
effect is</tt><tt><br>
</tt><tt> * that the reset button stops functioning. So</tt><tt><br>
</tt><tt> * instead just use outb so it doesn't output
to the</tt><tt><br>
</tt><tt> * console when CONFIG_CONSOLE_POST.</tt><tt><br>
</tt><tt> */</tt><tt><br>
</tt><tt> outb(0x40, 0x80);</tt><tt><br>
</tt><tt><br>
</tt><tt> /* Rangeley UART POR state is enabled */</tt><tt><br>
</tt><tt> console_init();</tt><tt><br>
</tt><tt> post_code(0x41);</tt><tt><br>
</tt><tt><br>
</tt><tt> /* Enable GPIOs BAR */</tt><tt><br>
</tt><tt> pci_write_config32(SOC_LPC_DEV, GBASE,
DEFAULT_GPIOBASE|0x02);</tt><tt><br>
</tt><tt><br>
</tt><tt> early_mainboard_romstage_entry();</tt><tt><br>
</tt><tt><br>
</tt><tt> post_code(0x42);</tt><tt><br>
</tt><tt> rangeley_sb_early_initialization();</tt><tt><br>
</tt><tt><br>
</tt><tt> post_code(0x46);</tt><tt><br>
</tt><tt> /* Program any required function disables */</tt><tt><br>
</tt><tt> get_func_disables(&fd_mask);</tt><tt><br>
</tt><tt><br>
</tt><tt> if (fd_mask != 0) {</tt><tt><br>
</tt><tt> write32(func_dis, read32(func_dis) |
fd_mask);</tt><tt><br>
</tt><tt> /* Ensure posted write hits. */</tt><tt><br>
</tt><tt> read32(func_dis);</tt><tt><br>
</tt><tt> }</tt><tt><br>
</tt><tt><br>
</tt><tt> /*</tt><tt><br>
</tt><tt> * Call early init to initialize memory and
chipset. This function returns</tt><tt><br>
</tt><tt> * to the romstage_main_continue function with a
pointer to the HOB</tt><tt><br>
</tt><tt> * structure.</tt><tt><br>
</tt><tt> */</tt><tt><br>
</tt><tt> post_code(0x47);</tt><tt><br>
</tt><tt> printk(BIOS_DEBUG, "Starting the Intel FSP
(early_init)\n");</tt><tt><br>
</tt><tt> fsp_early_init(fsp_info_header);</tt><tt><br>
</tt><tt> die("Uh Oh! fsp_early_init should not return
here.\n");</tt><tt><br>
</tt><tt>}</tt><tt><br>
</tt></small><br>
... and I'm affraid we get stucked in the fsp_early_init()
function ... :-(<br>
<br>
Regards.<br>
Patrick Agrain<br>
<br>
Le 11/03/2015 16:21, Patrick Agrain a écrit :<br>
</div>
<blockquote cite="mid:55005D6F.2010000@alcatel-lucent.com"
type="cite"> Hello Kyösti,<br>
<br>
I tried what you suggested below:<br>
<br>
- Enabled EARLY_PCI_BRIDGE<br>
- Set Bridge at D:1 F:0<br>
- Enabled OXI PCIe952 and disabled SERIAL_PORT_ON_SUPERIO.<br>
Reboot Mohon Peak CRB: failed. No output. POST code at 0xA9.<br>
<br>
Will try to get further. <br>
If anybody has an idea...<br>
<br>
Regards,<br>
Patrick Agrain<br>
<br>
<pre>On Fri, 2015-03-06 at 17:25 +0100, Patrick Agrain wrote:
><i> Hello everybody,
</i>><i>
</i>><i> Do you think that it would be possible to output the console messages
</i>><i> from coreboot (seabios) on another UART port (strapped to be visible on
</i>><i> Memory-based space or IO Space) connected on a PCIe slot ?
</i>><i>
</i>
Yes, it has been done before.
I should have a hack for SeaBIOS to support memory-mapped UART
somewhere, I will go and look. If I remember correctly SeaBIOS boot
media selection only works from local keyboard, not over serial.
><i> I've purchased a StarTech UART board with an OXPCIe952 chip, with the
</i>><i> same IDs as visible in ./src/drivers/uart/oxpcie.c.
</i>><i>
</i>><i> On
</i>><i> <a moz-do-not-send="true" href="http://www.coreboot.org/Serial_console#PCIe.2FMini_PCIe_based_serial_cards,">http://www.coreboot.org/Serial_console#PCIe.2FMini_PCIe_based_serial_cards,</a>
</i>><i> what is behind the sentence:
</i>><i> "In order to use the card for romstage debugging, minimal setup of the
</i>><i> PCIe bridge and the MPEX2S952 have to be added to romstage.c" ?
</i>><i>
</i>
You need to enable OxPCIe support and set EARLY_PCI_BRIDGE_* variables
in menuconfig. If you can boot to OS with that plaform, with the serial
card installed, get the location of PCIe rootport (aka. parent bridge)
for OxPCIe card with lspci -vv command.
Once you have OS shell, both coreboot and SeaBIOS console messages are
available from CBMEM console using 'cbmem -c' command.
><i> Thanks in advance.
</i>><i> Best regards,
</i>><i> Patrick Agrain
</i>><i>
</i>
HTH,
Kyösti</pre>
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