<p dir="ltr">Currently I'm porting coreboot for atom e6xx processor board.</p>
<p dir="ltr">This correction is a part of it.</p>
<p dir="ltr">Few more minor corrections to come.</p>
<p dir="ltr">Once I feel its fully stable and reliable then I'll update it in git.</p>
<p dir="ltr">My best try is to add the processor in coreboot supported procesor list</p>
<p dir="ltr">- N Solanki</p>
<div class="gmail_quote">On 23 Mar 2015 23:16, "ron minnich" <<a href="mailto:rminnich@gmail.com">rminnich@gmail.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Nice job, documents are almost always full of errors :-)<br><br>Any way you can create a patch for some part of some code base? This email will be forgotten quickly and we want<div>your hard-earned knowledge :-)</div><div><br></div><div>ron</div></div><br><div class="gmail_quote">On Mon, Mar 23, 2015 at 10:43 AM Naresh G. Solanki <<a href="mailto:naresh.solanki.2011@gmail.com" target="_blank">naresh.solanki.2011@gmail.com</a>> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><p dir="ltr">Hi All,</p>
<p dir="ltr">I was facing difficulty in enabling 0xE0000 & 0xF0000 segment on intel atom e6xx processor. </p>
<p dir="ltr">As per guide (atom e6xx minimum boot requirements) in table 15 it was mentioned that the segment can be enabled by setting bit 1 & 2 of port 0 reg offset 3. I tried but it failed.</p>
<p dir="ltr">I needed it to execute seabios successfully. </p>
<p dir="ltr">By trial & error I found that instead of port 0 if I tried setting the bits in port 2 offset 3 , it served my purpose completely.( I think its wrongly documented in the guide I was refering)</p>
<p dir="ltr">Now I'm able to execute seabios successfully. </p>
<p dir="ltr">This post is just for your information, if in case it can help any one.</p>
<p dir="ltr">Thank you for support.</p>
<p dir="ltr">- N Solanki</p>
<div class="gmail_quote">On 20 Mar 2015 21:03, "Naresh G. Solanki" <<a href="mailto:naresh.solanki.2011@gmail.com" target="_blank">naresh.solanki.2011@gmail.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><p dir="ltr">As per reply from seabios mailing list,<br>
the address range 0xE0000 to 0x10_0000 should have read write access and that can be done with help of some magic bit.</p>
<p dir="ltr">Does anyone knows about these magic bits.<br>
The processor I'm working with is atom e6xx.</p>
<p dir="ltr">-N Solanki<br>
</p>
<div class="gmail_quote">On 20 Mar 2015 19:24, "WANG FEI" <<a href="mailto:wangfei.jimei@gmail.com" target="_blank">wangfei.jimei@gmail.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">I'm curious why your seabios payload is loading to shadow RAM (C/D/E/F000 segment), this area suppose to be used by seabios, I guess since seabios is a legacy BIOS. My suggestion is to load your seabios to a over 1MB address.</div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Mar 19, 2015 at 2:38 PM, Naresh G. Solanki <span dir="ltr"><<a href="mailto:naresh.solanki.2011@gmail.com" target="_blank">naresh.solanki.2011@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hi All,<div><br></div><div><br></div><div><div>I'm trying to port coreboot with seabios payload.</div><div>Everything goes fine till the control is transferred to payload.</div><div><br></div><div>Since payload is loaded between memory range 0xC_0000 - 0x10_0000.</div><div><br></div><div>The problem I was facing was that the board was going to auto reboot mode while executing payload..</div><div><br></div><div>Once it reboot then I'm not able to control the processor through XDP until I manually do CPU reset.</div><div><br></div><div>It keeps on rebooting once control is transferred to payload.</div><div><br></div><div><br></div><div>To find out the cause I did detailed memory test & found out that the</div><div>memory range 0xA0000 - 0xBFFFF & 0xE0000 - 0xFFFFF always reads 0xFF.</div><div><br></div><div>since payload is loaded in the same region so before jmp_payload, I tried to read this region through XDP & found payload code exist.</div><div><br></div><div>so I introduced wbinvd instruction just before jmp_payload & I found that the XDP started reading 0xFF in the memory range 0xE0000 - 0xFFFFF.</div><div><br></div><div>Thus from this I conclude that before the payload was able to execute because of cached copy of it in CPU cache & it didn't really existed in RAM.</div><div><br></div><div>Also to enable memory range 0xE_0000 to 0xF_FFFF I have followed the guidlines as per table 15 of the document </div><div><a href="http://www.intel.com/content/www/us/en/intelligent-systems/queens-bay/atom-e6xx-boot-requirements-app-note.html" target="_blank">http://www.intel.com/content/www/us/en/intelligent-systems/queens-bay/atom-e6xx-boot-requirements-app-note.html</a><br></div><div><br></div><div>Is that OK.</div><div>What I can do to successfully enable the memory range 0xE_0000 to 0xF_FFFF for read write operation so that my payload execution goes undisturbed.</div><div><br></div><div>My ultimate aim is to load Windows by Seabios as payload.</div><div><br></div><div>Thanks</div><div>N Solanki</div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div>
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