<div dir="ltr">Sorry to follow up so soon - but just noticed an error in my post. I meant <i style="font-family:monospace,monospace;font-size:12.8px"><b>fallback/refcode </b></i>not <i>fallback/romstage, </i>which although still slightly different in size was at least built rather than extracted and re-inserted, and is at the same offset as the original.</div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Feb 23, 2016 at 3:41 PM, Marcos Scriven <span dir="ltr"><<a href="mailto:marcos@scriven.org" target="_blank">marcos@scriven.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div style="font-size:12.8px">Hi all</div><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">I've built a ROM for swanky which just results in a brick, and wondering if anyone else has had success with this (or any Bay Trail Chromebook), or could otherwise provide guidance please.</div><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">I've been able to reprogram the ROM directly, and am working with a patched boot stub region for now. I'm happy to experiment with ROM builds that will brick the machine (though annoyingly on the Toshiba Chromebook 2 the Winbond chip is just a little too close to the shielding/heatsink, so I have to take that off too (sadpanda)).</div><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">Some links for context:</div><div style="font-size:12.8px"><br></div><div style="font-size:12.8px"><blockquote style="margin:0px 0px 0px 40px;border:none;padding:0px">ROM build artifact: <a href="https://github.com/marcosscriven/chromebook-coreboot/releases/download/release-1456238351/swanky.rom" target="_blank">https://github.com/marcosscriven/chromebook-coreboot/releases/download/release-1456238351/swanky.rom</a><br></blockquote></div><blockquote style="margin:0px 0px 0px 40px;border:none;padding:0px"><span style="font-size:12.8px">Config: <a href="https://github.com/marcosscriven/chromebook-coreboot/blob/release-1456238351/build/boards/swanky/.config" target="_blank">https://github.com/marcosscriven/chromebook-coreboot/blob/release-1456238351/build/boards/swanky/.config</a></span></blockquote><blockquote style="font-size:12.8px;margin:0px 0px 0px 40px;border:none;padding:0px">Build script: <a href="https://github.com/marcosscriven/chromebook-coreboot/blob/release-1456238351/build/build_rom.sh" target="_blank">https://github.com/marcosscriven/chromebook-coreboot/blob/release-1456238351/build/build_rom.sh</a></blockquote><blockquote style="font-size:12.8px;margin:0px 0px 0px 40px;border:none;padding:0px">Build log: <a href="https://travis-ci.org/marcosscriven/chromebook-coreboot/builds/111222889#L2001" target="_blank">https://travis-ci.org/marcosscriven/chromebook-coreboot/builds/111222889#L2001</a></blockquote><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">(NB The build log is for multiple boards, and includes other full and boot stub builds, so use the log link above to the line where the full swanky rom build starts.)</div><div style="font-size:12.8px"><br></div><span style="font-size:12.8px">Here's the layout for the custom build:</span><div style="font-size:12.8px"><br></div><blockquote style="margin:0px 0px 0px 40px;border:none;padding:0px"><font face="monospace, monospace"><span style="font-size:12.8px"><i>vagrant@vagrant-ubuntu-trusty-64:~$ cbfstool swanky.rom print<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>swanky.rom: 8192 kB, bootblocksize 1184, romsize 8388608, offset 0x700000<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>alignment: 64 bytes, architecture: x86<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i><br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>Name Offset Type Size<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>cmos_layout.bin 0x700000 cmos_layout 1164<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>pci8086,0f31.rom 0x7004c0 optionrom 65536<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>cpu_microcode_blob.bin 0x710500 microcode 104448<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>config 0x729d80 raw 4555<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>fallback/refcode 0x72af80 stage 4171<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>etc/boot-menu-key 0x72c040 raw 1<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>etc/boot-menu-message 0x72c0c0 raw 27<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>(empty) 0x72c140 null 15896<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>fallback/romstage 0x72ff80 stage 35475<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>fallback/coreboot_ram 0x738a80 stage 74547<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>fallback/payload 0x74ae00 payload 103192<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>(empty) 0x764180 null 245272<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>mrc.bin 0x79ffc0 spd 70168<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>(empty) 0x7b1240 null 240984<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>spd.bin 0x7ebfc0 spd 1024<br></i></span></font><font face="monospace, monospace"><span style="font-size:12.8px"><i>(empty) 0x7ec400 null 79576</i></span></font></blockquote><div style="font-size:12.8px"><div><br></div><div>And here's the layout for a backup made via SPI directly on the chip (Implied <i><font face="monospace, monospace">0x700000 </font></i>offset):</div><div><br></div></div><blockquote style="font-size:12.8px;margin:0px 0px 0px 40px;border:none;padding:0px"><div><font face="monospace, monospace"><i>vagrant@vagrant-ubuntu-trusty-64:~$ cbfstool swanky-by-spi.bin print -r BOOT_STUB</i></font></div><div><font face="monospace, monospace"><i>Performing operation on 'BOOT_STUB' region...</i></font></div><div><font face="monospace, monospace"><i>Name Offset Type Size</i></font></div><div><font face="monospace, monospace"><i>cmos_layout.bin 0x0 cmos_layout 1164</i></font></div><div><font face="monospace, monospace"><i>pci8086,0f31.rom 0x4c0 optionrom 65536</i></font></div><div><font face="monospace, monospace"><i>cpu_microcode_blob.bin 0x10500 microcode 104448</i></font></div><div><font face="monospace, monospace"><i>config 0x29d80 raw 5259</i></font></div><div><font face="monospace, monospace"><i>fallback/vboot 0x2b240 stage 15518</i></font></div><div><font face="monospace, monospace"><i>(empty) 0x2ef40 null 4120</i></font></div><div><font face="monospace, monospace"><i>fallback/romstage 0x2ff80 stage 36458</i></font></div><div><font face="monospace, monospace"><i>fallback/coreboot_ram 0x38e80 stage 82415</i></font></div><div><font face="monospace, monospace"><i>fallback/refcode 0x4d0c0 stage 4296</i></font></div><div><font face="monospace, monospace"><i>fallback/payload 0x4e1c0 payload 67396</i></font></div><div><font face="monospace, monospace"><i>u-boot.dtb 0x5e940 mrc_cache 4842</i></font></div><div><font face="monospace, monospace"><i>(empty) 0x5fc80 null 258840</i></font></div><div><font face="monospace, monospace"><i>mrc.bin 0x9efc0 spd 70168</i></font></div><div><font face="monospace, monospace"><i>(empty) 0xb0240 null 245080</i></font></div><div><font face="monospace, monospace"><i>spd.bin 0xebfc0 spd 1024</i></font></div><div><font face="monospace, monospace"><i>(empty) 0xec400 null 78360</i></font></div></blockquote><br style="font-size:12.8px"><div style="font-size:12.8px">The labels, offsets, types, and sizes of all the various blobs looks fine <b>except <i style="font-size:12.8px;font-family:monospace,monospace">fallback/romstage</i></b><span style="font-size:12.8px"><b>.</b> (vboot and u-boot are gone as I don't need verification, which worked fine for my wolf build.)</span></div><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">I'm not sure why my build (from the same commit hash of Google's coreboot fork as in the config extracted from original rom) is placing that blob at a different offset? I can't see anything in the config that would affect that.</div><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">The more troubling thing is my refcode is a little smaller! I've extracted it from the shellball with this method here: <a href="https://github.com/marcosscriven/chromebook-coreboot/blob/release-1456238351/build/util/extract_blobs.sh#L56" target="_blank">https://github.com/marcosscriven/chromebook-coreboot/blob/release-1456238351/build/util/extract_blobs.sh#L56</a></div><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">So far as I can tell <i style="font-family:monospace,monospace;font-size:12.8px">fallback/refcode </i><span style="font-size:12.8px">is a (U)EFI blob, the failure of which I'd imagine would result in not booting from disk, but not entirely sure it's the reason I seeing nothing at all.</span></div><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">I guess the thing I'd find most helpful is guidance on <b>how to debug this</b> myself? Only two things I could find:</div><div style="font-size:12.8px"><br></div><blockquote style="margin:0px 0px 0px 40px;border:none;padding:0px"><div style="font-size:12.8px">1) A mention of 'USB to USB' in a 2013 Coreboot presentation: <a href="https://docs.google.com/presentation/d/1eGPMu03vCxIO0a3oNX8Hmij_Qwwz6R6ViFC_1HlHOYQ/edit#slide=id.gf4036fef_0177" target="_blank">https://docs.google.com/presentation/d/1eGPMu03vCxIO0a3oNX8Hmij_Qwwz6R6ViFC_1HlHOYQ/edit#slide=id.gf4036fef_0177</a></div></blockquote><blockquote style="margin:0px 0px 0px 40px;border:none;padding:0px"><div style="font-size:12.8px">It's not entirely clear how this works - so far as I can tell it's essentially USB OTG, where the Chromebook USB port could act as a client. I don't see though how the CPU sets that up before the ROM code even runs, unless it's some microcode in the processor itself?</div></blockquote><blockquote style="margin:0px 0px 0px 40px;border:none;padding:0px"><div style="font-size:12.8px"><br></div></blockquote><blockquote style="margin:0px 0px 0px 40px;border:none;padding:0px"><div style="font-size:12.8px">2) I've also seen mention of Servo, but I don't seen any such header on my board. Looking at a photo of the Acer C720 here, it does look like there's an oblong space with pads there, but that would be a hell of a surface mounting job: <a href="https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices/acer-c720-chromebook" target="_blank">https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices/acer-c720-chromebook</a></div></blockquote><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">I hope I've provided sufficient background info, but if anyone's willing or able to help, I'd of course be happy to add more detail.</div><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">Thanks</div><span class="HOEnZb"><font color="#888888"><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">Marcos</div></font></span></div>
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