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--></style></head><body lang=DE-CH link=blue vlink="#954F72"><div class=WordSection1><p class=MsoNormal>Hi guys</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>I tried now with the latest coreboot 4.3 to run the coreboot bios on a Alix2d3. But it always hangs after: «* DRAM Controller init done.». After this i do not see any further Output. Does anyone of you have a an idea what could be the issue?</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>I added a ipxe Rom Image to the coreboot Rom. The layout is as follows: </p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Name Offset Type Size</p><p class=MsoNormal>cbfs master header 0x0 cbfs header 32</p><p class=MsoNormal>fallback/romstage 0x80 stage 12404</p><p class=MsoNormal>fallback/ramstage 0x3180 stage 69972</p><p class=MsoNormal>fallback/payload 0x14340 payload 60882</p><p class=MsoNormal>pci1106,3053.rom 0x23180 raw 81920</p><p class=MsoNormal>config 0x37200 raw 428</p><p class=MsoNormal>revision 0x37400 raw 602</p><p class=MsoNormal>payload_config 0x376c0 raw 1563</p><p class=MsoNormal>payload_revision 0x37d40 raw 219</p><p class=MsoNormal>vsa 0x37e80 stage 57532</p><p class=MsoNormal>(empty) 0x45f80 null 236568</p><p class=MsoNormal>bootblock 0x7fbc0 bootblock 768</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>The config file with the build Options can be found here: </p><p class=MsoNormal><a href="https://file.youngsolutions.ch/index.php/s/MrXbSGYdS5E8DsH">https://file.youngsolutions.ch/index.php/s/MrXbSGYdS5E8DsH</a></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Here a trace of the full Output:</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Setup throttling delays to proper mode</p><p class=MsoNormal>Done cpuRegInit</p><p class=MsoNormal>Ram1.00</p><p class=MsoNormal>Ram2.00</p><p class=MsoNormal> * sdram_set_spd_register</p><p class=MsoNormal>spd_read_byte dev 50 addr 15 returns ff</p><p class=MsoNormal> * Check DIMM 0</p><p class=MsoNormal> * Check DIMM 1</p><p class=MsoNormal>spd_read_byte dev 51 returns 0xff</p><p class=MsoNormal> * Check DDR MAX</p><p class=MsoNormal>spd_read_byte dev 50 addr 09 returns 0a</p><p class=MsoNormal>spd_read_byte dev 51 returns 0xff</p><p class=MsoNormal> * AUTOSIZE DIMM 0</p><p class=MsoNormal> * Check present</p><p class=MsoNormal>spd_read_byte dev 50 addr 02 returns 07</p><p class=MsoNormal> * MODBANKS</p><p class=MsoNormal>spd_read_byte dev 50 addr 05 returns 01</p><p class=MsoNormal> * FIELDBANKS</p><p class=MsoNormal>spd_read_byte dev 50 addr 11 returns 04</p><p class=MsoNormal> * SPDNUMROWS</p><p class=MsoNormal>spd_read_byte dev 50 addr 03 returns 03</p><p class=MsoNormal>spd_read_byte dev 50 addr 04 returns 0a</p><p class=MsoNormal> * SPDBANKDENSITY</p><p class=MsoNormal>spd_read_byte dev 50 addr 1f returns 40</p><p class=MsoNormal> * DIMMSIZE</p><p class=MsoNormal> * BEFORT CTZ</p><p class=MsoNormal> * TEST DIMM SIZE>8</p><p class=MsoNormal> * PAGESIZE</p><p class=MsoNormal>spd_read_byte dev 50 addr 04 returns 0a</p><p class=MsoNormal> * MAXCOLADDR</p><p class=MsoNormal> * >12address test</p><p class=MsoNormal> * RDMSR CF07</p><p class=MsoNormal> * WRMSR CF07</p><p class=MsoNormal> * ALL DONE</p><p class=MsoNormal> * AUTOSIZE DIMM 1</p><p class=MsoNormal> * Check present</p><p class=MsoNormal>spd_read_byte dev 51 returns 0xff</p><p class=MsoNormal> * set cas latency</p><p class=MsoNormal>spd_read_byte dev 50 addr 12 returns 10</p><p class=MsoNormal>spd_read_byte dev 50 addr 17 returns 3c</p><p class=MsoNormal>spd_read_byte dev 50 addr 19 returns 4b</p><p class=MsoNormal>spd_read_byte dev 51 returns 0xff</p><p class=MsoNormal> * set all latency</p><p class=MsoNormal>spd_read_byte dev 50 addr 1e returns 28</p><p class=MsoNormal>spd_read_byte dev 51 returns 0xff</p><p class=MsoNormal>spd_read_byte dev 50 addr 1b returns 0f</p><p class=MsoNormal>spd_read_byte dev 51 returns 0xff</p><p class=MsoNormal>spd_read_byte dev 50 addr 1d returns 0f</p><p class=MsoNormal>spd_read_byte dev 51 returns 0xff</p><p class=MsoNormal>spd_read_byte dev 50 addr 1c returns 0a</p><p class=MsoNormal>spd_read_byte dev 51 returns 0xff</p><p class=MsoNormal>spd_read_byte dev 50 addr 2a returns 46</p><p class=MsoNormal>spd_read_byte dev 51 returns 0xff</p><p class=MsoNormal> * set emrs</p><p class=MsoNormal>spd_read_byte dev 50 addr 16 returns ff</p><p class=MsoNormal>spd_read_byte dev 51 returns 0xff</p><p class=MsoNormal> * set ref rate</p><p class=MsoNormal>spd_read_byte dev 50 addr 0c returns 3a</p><p class=MsoNormal>spd_read_byte dev 51 returns 0xff</p><p class=MsoNormal>Ram3</p><p class=MsoNormal> * DRAM controller init done.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Gesendet von <a href="https://go.microsoft.com/fwlink/?LinkId=550986">Mail</a> für Windows 10</p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Times New Roman",serif'><o:p> </o:p></span></p></div></body></html>