<div dir="ltr">Thanks guys for help.<br><br>i have figured it out in my case. I have moved the cpu micro code binary(<span style="font-size:12.8px">cpu_microcode_blob.bin 0xe3fc0 microcode 137232</span>) to the empty space (<span style="font-size:12.8px">(empty) 0x150000 null 311192</span>) by which i am able to build the coreboot with the debug payload. for moving cpu micro code binary we need to adjust the location of cpu micro code in the Kconfig file such that it goes to empty space.<div><br><br><div style="font-size:12.8px">Name Offset Type Size</div><div style="font-size:12.8px">bootsplash.img 0x0 bootsplash 37443</div><div style="font-size:12.8px">cmos_layout.bin 0x9280 cmos_layout 1132</div><div style="font-size:12.8px">fspd.bin 0x9740 (unknown) 4608</div><div style="font-size:12.8px">fallback/ramstage 0xa980 stage 67423</div><div style="font-size:12.8px">fallback/payload 0x1b140 payload 769955</div><div style="font-size:12.8px">config 0xd7140 raw 4623</div><div style="font-size:12.8px">(empty) 0xd8380 null 48152</div><div style="font-size:12.8px">cpu_microcode_blob.bin 0xe3fc0 microcode 137232</div><div style="font-size:12.8px">(empty) 0x105840 null 1880</div><div style="font-size:12.8px">mrc.cache 0x105fc0 (unknown) 32768</div><div style="font-size:12.8px">(empty) 0x10e000 null 8088</div><div style="font-size:12.8px">uefi_nvs.bin 0x10ffc0 (unknown) 262144</div><div style="font-size:12.8px">(empty) 0x150000 null 311192</div><div style="font-size:12.8px">fsp.bin 0x19bfc0 (unknown) 314368</div><div style="font-size:12.8px">(empty) 0x1e8c00 null 58200</div><div style="font-size:12.8px">fallback/romstage 0x1f6f80 stage 35253</div><div style="font-size:12.8px">(empty) 0x1ff9c0 null 536</div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Apr 8, 2016 at 11:32 PM, Jay Talbott <span dir="ltr"><<a href="mailto:JayTalbott@sysproconsulting.com" target="_blank">JayTalbott@sysproconsulting.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">The FSP is rebased with the Intel BCT tool, not the FITC tool.<br>
<div class="HOEnZb"><div class="h5"><br>
> On Apr 8, 2016, at 7:38 AM, Martin Roth <<a href="mailto:gaumless@gmail.com">gaumless@gmail.com</a>> wrote:<br>
><br>
> Not knowing which platform this is makes it a little harder to<br>
> determine what's locked in place. We'd also need to know if this is<br>
> getting built from the top of the <a href="http://coreboot.org" rel="noreferrer" target="_blank">coreboot.org</a> tree, an old<br>
> <a href="http://coreboot.org" rel="noreferrer" target="_blank">coreboot.org</a> commit or an private repo with many changes from<br>
> <a href="http://coreboot.org" rel="noreferrer" target="_blank">coreboot.org</a>.<br>
><br>
> Microcode should be able to be placed in any area for most of the FSP<br>
> platforms, but it might need to be changed in Kconfig or the Makefile<br>
> so that the system knows where it is. You might also want to look at<br>
> just including the necessary microcode patches for your particular<br>
> board if possible. Many of the FSP platforms include all available<br>
> microcode back to some pre-production parts by default.<br>
><br>
> The mrc cache can be moved at build time, but needs to be on the<br>
> correct boundary, and CANNOT have anything else in the same sector on<br>
> the flash. The cache gets erased, so moving it to an odd boundary or<br>
> putting other things in the same sector will cause interesting issues.<br>
><br>
> The FSP itself can also be moved, but it needs to be rebased with<br>
> intel's FITC tool, and coreboot needs to know the location at build<br>
> time.<br>
><br>
> Finally, you might want to look at leaving out the small or<br>
> non-essential files, and add them after the build completes to make<br>
> sure that there is contiguous space for your essential components:<br>
> bootsplash.img, config, fspd.bin and cmos_layout.bin<br>
><br>
> Martin<br>
><br>
> On Fri, Apr 8, 2016 at 4:29 AM, Patrick Georgi via coreboot<br>
> <<a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a>> wrote:<br>
>> 2016-04-08 11:17 GMT+02:00 Nico Huber <<a href="mailto:nico.huber@secunet.com">nico.huber@secunet.com</a>>:<br>
>>> you also stripped:<br>
>>><br>
>>> fallback/payload 0x1b140 payload 769955<br>
>>><br>
>>> I guess he means that a fresh build with a bigger (865KiB instead of<br>
>>> 752KiB) payload fails.<br>
>> Of course you're right. I misunderstood the original issue.<br>
>><br>
>> It's hard to tell how locked down various files are. There's at least<br>
>> some alignment going on for cpu_microcode_blob.bin, mrc.cache,<br>
>> uefi_nvs.bin and fsp.bin, but there may be more to it.<br>
>><br>
>> Tweaking -position and -align values for mrc.cache and uefi_nvs.bin<br>
>> should provide enough space for a larger payload.<br>
>> Given that uefi_nvs.bin is not mentioned in current master, I have no<br>
>> idea how that came to be.<br>
>><br>
>><br>
>> Patrick<br>
>><br>
>> --<br>
>> coreboot mailing list: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
>> <a href="https://www.coreboot.org/mailman/listinfo/coreboot" rel="noreferrer" target="_blank">https://www.coreboot.org/mailman/listinfo/coreboot</a><br>
><br>
> --<br>
> coreboot mailing list: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
> <a href="https://www.coreboot.org/mailman/listinfo/coreboot" rel="noreferrer" target="_blank">https://www.coreboot.org/mailman/listinfo/coreboot</a><br>
><br>
</div></div></blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature">Thanks,<div>Rajashaker Goud Ranga</div></div>
</div>