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<p class="MsoNormal"><span style="color:#1F497D">Here is final Coreboot image info with debug FSP.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">Performing operation on 'COREBOOT' region...<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">Name Offset Type Size<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">cbfs master header 0x0 cbfs header 32<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">fallback/romstage 0x80 stage 29996<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">config 0x7640 raw 515<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">revision 0x7880 raw 570<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">cmos_layout.bin 0x7b00 cmos_layout 1096<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">fallback/dsdt.aml 0x7f80 raw 12465<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">payload_config 0xb080 raw 1563<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">payload_revision 0xb700 raw 267<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">(empty) 0xb880 null 17944<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">mrc.cache 0xfec0 mrc_cache 65536<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">cpu_microcode_blob.bin 0x1ff00 microcode 208896<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">fallback/ramstage 0x52f80 stage 54702<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">fallback/payload 0x60580 payload 63348<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">pci8086,0f31.rom 0x6fd40 optionrom 65536<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">(empty) 0x7fdc0 null 1245400<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">fsp.bin 0x1afec0 fsp 294912<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">(empty) 0x1f7f00 null 31064<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">bootblock 0x1ff880 bootblock 1560<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">Built intel/bayleybay_fsp (Bayley Bay CRB (FSP))<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">Thanks,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">Kathappan <o:p></o:p></span></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="mso-fareast-language:EN-IN">From:</span></b><span lang="EN-US" style="mso-fareast-language:EN-IN"> Kathappan E
<br>
<b>Sent:</b> 09 May 2016 12:35<br>
<b>To:</b> 'Aaron Durbin' <adurbin@google.com>; 'Zoran Stojsavljevic' <zoran.stojsavljevic@gmail.com><br>
<b>Cc:</b> coreboot@coreboot.org<br>
<b>Subject:</b> RE: [coreboot] Unable to build coreboot with Intel FSP debug binary on BayleyBay<o:p></o:p></span></p>
</div>
</div>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoPlainText">Hi Aaron/Zoran,<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Thank you for your inputs.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">After adjusting <b>FSP_LOC</b> Kconfig (Intel FSP Binary location in CBFS in
<i>menuconfig</i>) variable as it is configured in FSP binary, coreboot is getting build with debug FSP binary.
<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">I see the base location of FSP binary using BCT tool as below.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Release FSP Binary (BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd) ==> 0xFFFC0000<o:p></o:p></p>
<p class="MsoPlainText">Debug FSP Binary (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd) ==> 0xFFFB0000<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Thanks,<o:p></o:p></p>
<p class="MsoPlainText">Kathappan<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><span lang="EN-US" style="mso-fareast-language:EN-IN">-----Original Message-----<br>
From: Aaron Durbin [<a href="mailto:adurbin@google.com">mailto:adurbin@google.com</a>]
<br>
Sent: 06 May 2016 19:47<br>
To: Kathappan E <<a href="mailto:Kathappan.E@LntTechservices.com">Kathappan.E@LntTechservices.com</a>><br>
Cc: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
Subject: Re: [coreboot] Unable to build coreboot with Intel FSP debug binary on BayleyBay</span><o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">On Fri, May 6, 2016 at 12:39 AM, Kathappan E <<a href="mailto:Kathappan.E@lnttechservices.com"><span style="color:windowtext;text-decoration:none">Kathappan.E@lnttechservices.com</span></a>> wrote:<o:p></o:p></p>
<p class="MsoPlainText">> Hi all,<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> I am able to build Coreboot with FSP Baytrail release <o:p>
</o:p></p>
<p class="MsoPlainText">> binary(BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd).<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> But I am unable to build with FSP Baytrail debug binary<o:p></o:p></p>
<p class="MsoPlainText">> (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd) and it throws the below
<o:p></o:p></p>
<p class="MsoPlainText">> error says that binary size is large and fails to add into image.<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> The sections containing CBFSes are: COREBOOT<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> Performing operation on 'COREBOOT' region...<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> Created CBFS (capacity = 2096856 bytes)<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> Performing operation on 'COREBOOT' region...<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> Performing operation on 'COREBOOT' region...<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> CBFS fsp.bin<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> Performing operation on 'COREBOOT' region...<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> E: Not enough space for content.<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> E: Could not add [fsp, 294912 bytes (288 KB)@0x1bff00]; too big?<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> E: Failed to add '../intel/fsp/baytrail/BAYTRAIL_FSP_D.fd' into ROM image.<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> E: Failed while operating on 'COREBOOT' region!<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> E: The image will be left unmodified.<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> make: *** [build/coreboot.pre] Error 1<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> Can you please anyone help me on this?<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">You likely need to adjust the FSP_LOC kconfig variable to match the debug FSP binary. Most likely the debug binary is large and not linked at the same address which in this case breaks building because there's not enough flash space.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> Thanks in advance,<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> Kathappan<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> L&T Technology Services Ltd<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
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