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<p class="MsoNormal">Hi,</p>
<p class="MsoNormal">I am bringing up a new board using coreboot as the bios.</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">Hardware:</p>
<p class="MsoListParagraph" style="text-indent:-18.0pt"><span style="">-<span style="font:7.0pt "Times New Roman"">
</span></span> Based on Intel Valley Island design (which has TPE)</p>
<p class="MsoListParagraph" style="text-indent:-18.0pt"><span style="">-<span style="font:7.0pt "Times New Roman"">
</span></span>No TPM</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">Coreboot:</p>
<p class="MsoListParagraph" style="text-indent:-18.0pt"><span style="">-<span style="font:7.0pt "Times New Roman"">
</span></span>Source coreboot 4.4 release </p>
<p class="MsoListParagraph" style="text-indent:-18.0pt"><span style="">-<span style="font:7.0pt "Times New Roman"">
</span></span>Using code based on Bayley bay (Intel FSP)</p>
<p class="MsoListParagraph" style="text-indent:-18.0pt"><span style="">-<span style="font:7.0pt "Times New Roman"">
</span></span>FSP: Gold3</p>
<p class="MsoListParagraph" style="text-indent:-18.0pt"><span style="">-<span style="font:7.0pt "Times New Roman"">
</span></span>Using a bios based on Valley Island for the non-coreboot sections</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">The board boots, goes through romstage and then freezes early in the ramstage (before enabling any devices): see output below</p>
<p class="MsoNormal">To me it seems there may be a hardware issue (new board, I am suspecting memory) but I thought I would ask as someone may have seen something similar.</p>
<p class="MsoNormal"> </p>
<p class="MsoListParagraph" style="text-indent:-18.0pt"><span style="">1)<span style="font:7.0pt "Times New Roman"">
</span></span>Could the non coreboot part of the bios chip cause this.</p>
<p class="MsoListParagraph" style="text-indent:-18.0pt"><span style="">2)<span style="font:7.0pt "Times New Roman"">
</span></span>Is there a way to check memory at the rom stage.</p>
<p class="MsoListParagraph" style="text-indent:-18.0pt"><span style="">3)<span style="font:7.0pt "Times New Roman"">
</span></span>Is there any information on the memory map of the bios chip.</p>
<p class="MsoListParagraph" style="text-indent:-18.0pt"><span style="">4)<span style="font:7.0pt "Times New Roman"">
</span></span>Is there a way to check other devices at the romstage or early ram stage.</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">I have tried skipping the “Enumeratin busses” section but it just crashes at the next stage (I guess I cannot really expect ti to get very far without its busses).</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">Note: I am new to coreboot and bios development in general.</p>
<p class="MsoNormal">Any help, suggestion appreciated.</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">Output Log:</p>
<p class="MsoNormal">--------------------------------------</p>
<p class="MsoNormal">coreboot-099d78c-dirty Thu May 12 05:41:22 UTC 2016 romstage starting...</p>
<p class="MsoNormal">RTC Init</p>
<p class="MsoNormal">POST: 0x44</p>
<p class="MsoNormal">POST: 0x47</p>
<p class="MsoNormal">POST: 0x48</p>
<p class="MsoNormal">Starting the Intel FSP (early_init)</p>
<p class="MsoNormal">PM1_STS = 0x100 PM1_CNT = 0x0 GEN_PMCON1 = 0x45008</p>
<p class="MsoNormal">prev_sleep_state = S5</p>
<p class="MsoNormal">Configure Default UPD Data</p>
<p class="MsoNormal">PcdMrcInitSPDAddr1: 0xa0 (default)</p>
<p class="MsoNormal">PcdMrcInitSPDAddr2: 0xa2 (default)</p>
<p class="MsoNormal">PcdSataMode: 0x01 (set)</p>
<p class="MsoNormal">PcdLpssSioEnablePciMode: 0x01 (default)</p>
<p class="MsoNormal">PcdMrcInitMmioSize: 0x800 (default)</p>
<p class="MsoNormal">PcdIgdDvmt50PreAlloc: 0x02 (default)</p>
<p class="MsoNormal">PcdApertureSize: 0x02 (default)</p>
<p class="MsoNormal">PcdGttSize: 0x02 (default)</p>
<p class="MsoNormal">SerialDebugPortAddress: 0x3f8 (default)</p>
<p class="MsoNormal">SerialDebugPortType: 0x01 (default)</p>
<p class="MsoNormal">PcdMrcDebugMsg: 0x00 (default)</p>
<p class="MsoNormal">PcdSccEnablePciMode: 0x01 (default)</p>
<p class="MsoNormal">IgdRenderStandby: 0x00 (default)</p>
<p class="MsoNormal">TxeUmaEnable: 0x00 (default)</p>
<p class="MsoNormal">PcdOsSelection: 0x04 (default)</p>
<p class="MsoNormal">PcdEMMC45DDR50Enabled: 0x01 (default)</p>
<p class="MsoNormal">PcdEMMC45HS200Enabled: 0x00 (default)</p>
<p class="MsoNormal">PcdEMMC45RetuneTimerValue: 0x08 (default)</p>
<p class="MsoNormal">PcdEnableIgd: 0x00 (default)</p>
<p class="MsoNormal">AutoSelfRefreshEnable: 0x00 (default)</p>
<p class="MsoNormal">APTaskTimeoutCnt: 0x00 (default)</p>
<p class="MsoNormal">GTT Size: 2 MB</p>
<p class="MsoNormal">Tseg Size: 8 MB</p>
<p class="MsoNormal">Aperture Size: 256 MB</p>
<p class="MsoNormal">IGD Memory Size: 64 MB</p>
<p class="MsoNormal">MMIO Size: 2048 MB</p>
<p class="MsoNormal">MIPI/ISP: Disabled</p>
<p class="MsoNormal">Sdio: Enabled</p>
<p class="MsoNormal">Sdcard: Enabled</p>
<p class="MsoNormal">SATA: Enabled</p>
<p class="MsoNormal">SIO Dma 0: Enabled</p>
<p class="MsoNormal">SIO I2C0: Enabled</p>
<p class="MsoNormal">SIO I2C1: Enabled</p>
<p class="MsoNormal">SIO I2C2: Enabled</p>
<p class="MsoNormal">SIO I2C3: Enabled</p>
<p class="MsoNormal">SIO I2C4: Enabled</p>
<p class="MsoNormal">SIO I2C5: Enabled</p>
<p class="MsoNormal">SIO I2C6: Enabled</p>
<p class="MsoNormal">Azalia: Enabled</p>
<p class="MsoNormal">SIO Dma1: Enabled</p>
<p class="MsoNormal">Pwm0: Enabled</p>
<p class="MsoNormal">Pwm1: Enabled</p>
<p class="MsoNormal">Hsuart0: Enabled</p>
<p class="MsoNormal">Hsuart1: Enabled</p>
<p class="MsoNormal">Spi: Enabled</p>
<p class="MsoNormal">Lpe: Disabled</p>
<p class="MsoNormal">eMMC Mode: eMMC 4.5</p>
<p class="MsoNormal">SATA Mode: AHCI</p>
<p class="MsoNormal">Xhci: Enabled</p>
<p class="MsoNormal">CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)</p>
<p class="MsoNormal">CBFS: Locating 'mrc.cache'</p>
<p class="MsoNormal">CBFS: Found @ offset fec0 size 10000</p>
<p class="MsoNormal">find_current_mrc_cache_local: No valid fast boot cache found.</p>
<p class="MsoNormal">FSP MRC cache not present.</p>
<p class="MsoNormal">POST: 0x92</p>
<p class="MsoNormal">POST: 0x4a</p>
<p class="MsoNormal">romstage_main_continue status: 0 hob_list_ptr: 7ae20000</p>
<p class="MsoNormal">FSP Status: 0x0</p>
<p class="MsoNormal">PM1_STS = 0x101 PM1_CNT = 0x0 GEN_PMCON1 = 0x1001808</p>
<p class="MsoNormal">romstage_main_continue: prev_sleep_state = S0</p>
<p class="MsoNormal">Baytrail Chip Variant: Bay Trail-I (ISG/embedded)</p>
<p class="MsoNormal">MRC v0.100</p>
<p class="MsoNormal">2 channels of DDR3 @ 1333MHz</p>
<p class="MsoNormal">POST: 0x4b</p>
<p class="MsoNormal">POST: 0x4c</p>
<p class="MsoNormal">POST: 0x4d</p>
<p class="MsoNormal">CBMEM:</p>
<p class="MsoNormal">IMD: root @ 7adff000 254 entries.</p>
<p class="MsoNormal">IMD: root @ 7adfec00 62 entries.</p>
<p class="MsoNormal">POST: 0x4e</p>
<p class="MsoNormal">POST: 0x4f</p>
<p class="MsoNormal">CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)</p>
<p class="MsoNormal">CBFS: Locating 'fallback/ramstage'</p>
<p class="MsoNormal">CBFS: Found @ offset 46380 size d5be</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">coreboot-099d78c-dirty Thu May 12 05:41:22 UTC 2016 ramstage starting...</p>
<p class="MsoNormal">POST: 0x39</p>
<p class="MsoNormal">Moving GDT to 7adfe9c0...ok</p>
<p class="MsoNormal">POST: 0x80</p>
<p class="MsoNormal">POST: 0x70</p>
<p class="MsoNormal">BS: BS_PRE_DEVICE times (us): entry 0 run 1168 exit 0</p>
<p class="MsoNormal">POST: 0x71</p>
<p class="MsoNormal">CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)</p>
<p class="MsoNormal">CBFS: Locating 'cpu_microcode_blob.bin'</p>
<p class="MsoNormal">CBFS: Found @ offset 1ff00 size 26400</p>
<p class="MsoNormal">microcode: sig=0x30679 pf=0x1 revision=0x901</p>
<p class="MsoNormal">CPUID: 00030679</p>
<p class="MsoNormal">Cores: 4</p>
<p class="MsoNormal">Revision ID: 11</p>
<p class="MsoNormal">Stepping: D0</p>
<p class="MsoNormal">msr(17) = 0000000090041743</p>
<p class="MsoNormal">msr(ce) = 0000060000001700</p>
<p class="MsoNormal">BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 30606 exit 0</p>
<p class="MsoNormal">POST: 0x72</p>
<p class="MsoNormal">Enumerating buses...</p>
<p class="MsoNormal">Show all devs... Before device enumeration.</p>
<p class="MsoNormal">Root Dev</p>
<p class="MsoNormal">----------------------------</p>
</div>
<p style="font-size:10pt; font-family:"Tahoma","sans-serif"; color:#595959"><b>Naveed Ghori</b> | Lead Firmware & Driver Engineer
</p>
<p style="font-size:10pt; font-family:"Tahoma","sans-serif"; color:#595959"><b>DTI Group Ltd</b> |
<b><span style="font-size:7.5pt; font-family:"Tahoma","sans-serif"; color:#E36C0A">Transit Security & Surveillance</span></b></p>
<p style="font-size:7.5pt; font-family:"Tahoma","sans-serif"; color:#595959">31 Affleck Road, Perth Airport, Western Australia 6105, AU</p>
<p style="font-size:7.5pt; font-family:"Tahoma","sans-serif"; color:#595959">P +61 8 9373 2905,151 | F +61 8 9479 1190 | naveed.ghori@dti.com.au
</p>
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