<div dir="ltr">It's great to hear this! Thanks sharing the knowledge with coreboot community, enjoy your coreboot/FSP journey.</div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, May 17, 2016 at 2:39 AM, 김유석 <span dir="ltr"><<a href="mailto:poplinux0@gmail.com" target="_blank">poplinux0@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div bgcolor="#FFFFFF" text="#000000">
<div>Dear Sir.<br>
<br>
Thank's your advise.<br>
<br>
I was solved this issue.<br>
<br>
The cause was "Image size".<br>
<br>
My spi flash is have a 16MByte size. and coreboot.rom's size is a
2MByte.<br>
<br>
And I was write from 0x00. But x86 is must write from bottom. I
guess.<br>
<br>
<br>
<b>For example</b><br>
<br>
case 1.<br>
coreboot image : 2MByte<br>
flash storage : 16MByte<br>
<br>
You must write start address is 0x00E00000(offset 14MByte)<br>
<br>
case 2.<br>
coreboot image : 8MByte<br>
flash storage : 16MByte<br>
<br>
You must write start address is 0x00800000(offset 8MByte)<br>
<br>
case 3.<br>
coreboot image : 16MByte<br>
flash storage : 16MByte<br>
<br>
You must write start address is 0x00000000(offset 0MByte)<br>
<br>
<br>
This time, coreboot work is very fine.<br>
<br>
Thank you.<br>
<br>
2016-02-04 오후 11:02에 WANG FEI 이(가) 쓴 글:<br>
</div><div><div class="h5">
<blockquote type="cite">
<div dir="ltr"><b style="font-size:10.6667px">RANGELEY_POSTGOLD4_FSP_004_20150924.fd
is the FSP binary, you can rename it to FvFsp.bin and placed
it to the path defined in coreboot, ie, </b><span style="font-size:10.6667px">`../intel/fsp/rangeley/Fv<b>, to
generate coreboot image.</b></span><br>
</div>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Thu, Feb 4, 2016 at 5:19 AM, 김유석 <span dir="ltr"><<a href="mailto:poplinux0@gmail.com" target="_blank">poplinux0@gmail.com</a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div text="#000000" bgcolor="#FFFFFF">
<div>Dear Martin.<br>
<br>
Thank's your advise. <br>
<br>
I'm use the serial consol port. but can't see any
message. <br>
<br>
Thank you.<br>
<br>
2016-02-02 오후 9:18에 Martin Roth 이(가) 쓴 글:<br>
</div>
<div>
<div>
<blockquote type="cite">You might try a different
video card. There's an issue in the video bios of
the aspeed card that came with the mohon peak.<br>
<br>
martin<br>
<div class="gmail_quote">
<div dir="ltr">On Tue, Feb 2, 2016 at 00:41 김유석
<<a href="mailto:poplinux0@gmail.com" target="_blank">poplinux0@gmail.com</a>>
wrote:<br>
</div>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div text="#000000" bgcolor="#FFFFFF"> <font face="굴림체">Dear sir. <br>
<br>
My ENV is see below.<br>
<br>
<b>EVB : Intel rangeley Mohon Peak CRB</b><br>
<br>
<br>
<font color="#ff0000">This time</font>, I
was download the coreboot from git.<br>
<br>
<small> poplinux@raw work $ > git clone
<a href="http://review.coreboot.org/coreboot.git" target="_blank">http://review.coreboot.org/coreboot.git</a>
./<br>
</small></font><small><font face="굴림체"><font face="굴림체">poplinux@raw work $ > </font>cd
coreboot<br>
</font></small><font face="굴림체"><small><font face="굴림체">poplinux@raw coreboot $ >
</font>git submodule update --init
--checkout</small><br>
<br>
<font color="#ff0000">Next,</font> <b>run
make menuconfig</b> and set-up to mohon
peak CRB and save & exit<br>
<br>
<small><b> Mainboa</b><b>rd</b><br>
Mainboard vendor (<b>Intel</b>)
---> <br>
Mainboard model (<b>Mohon Peak CRB</b>)
---><br>
[ ] Configure defaults for the Intel
FSP package <br>
ROM chip size (2048 KB (2 MB))
---> <br>
(0x00200000) Size of CBFS filesystem in
ROM <br>
() fmap description file in fmd format</small><br>
<br>
<font color="#ff0000">Next,</font> I'm try
to build core boot. <br>
<br>
<small> poplinux@raw coreboot $ > make<br>
GEN generated/bootblock.ld<br>
CP
bootblock/arch/x86/bootblock.ld<br>
LINK
cbfs/fallback/bootblock.debug<br>
OBJCOPY cbfs/fallback/bootblock.elf<br>
OBJCOPY bootblock.raw.bin<br>
Checking out SeaBIOS revision
01a84bea2d28a19d2405c1ecac4bdef17683cc0c<br>
Switched to branch 'master'<br>
<br>
Performing operation on 'COREBOOT'
region...<br>
Name
Offset Type Size<br>
cbfs master header
0x0 cbfs header 32<br>
fallback/romstage
0x80 stage 22684<br>
cpu_microcode_blob.bin
0x5980 microcode 0<br>
config
0x5a00 raw 127<br>
revision
0x5ac0 raw 570<br>
cmos_layout.bin
0x5d40 cmos_layout 1316<br>
fallback/dsdt.aml
0x62c0 raw 7952<br>
payload_config
0x8240 raw 1574<br>
payload_revision
0x88c0 raw 237<br>
(empty)
0x8a00 null 29848<br>
mrc.cache
0xfec0 mrc_cache 65536<br>
fallback/ramstage
0x1ff00 stage 46922<br>
fallback/payload
0x2b6c0 payload 61122<br>
(empty)
0x3a5c0 null 1856216<br>
bootblock
0x1ff8c0 bootblock 1528</small><br>
<br>
<font color="#ff0000">Finally,</font> I'm
got a coreboot image.<br>
</font><br>
<font face="굴림체"><br>
<small> poplinux@raw build $ > ls
build/coreboot.rom <br>
build/coreboot.rom<br>
poplinux@raw build $ >
./build/cbfstool build/coreboot.rom print<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>Performing
operation on 'COREBOOT' region...<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>Name
Offset Type Size<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>cbfs
master header 0x0 cbfs
header 32<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>fallback/romstage
0x80 stage 22684<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>cpu_microcode_blob.bin
0x5980 microcode 0<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>config
0x5a00 raw 127<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>revision
0x5ac0 raw 570<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>cmos_layout.bin
0x5d40 cmos_layout 1316<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>fallback/dsdt.aml
0x62c0 raw 7952<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>payload_config
0x8240 raw 1574<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>payload_revision
0x88c0 raw 237<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>(empty)
0x8a00 null 29848<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>mrc.cache
0xfec0 mrc_cache 65536<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>fallback/ramstage
0x1ff00 stage 46922<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>fallback/payload
0x2b6c0 payload 61122<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>(empty)
0x3a5c0 null 1856216<br>
</small></font><font face="굴림체"><small><font face="굴림체"><small> </small></font>bootblock
0x1ff8c0 bootblock 1528</small><br>
<br>
<br>
<font color="#ff0000">And</font> I'm write
image to my EVB using <b>ALL-100 Gang-writ</b><b>er</b>.<br>
spi flash's write <b>start address is set
0x00000000</b>. write it success.<br>
<br>
<font color="#ff0000">And</font> I'm attach
the flash memory to my EVB.<br>
<br>
<font color="#ff0000">And </font>power-up
the my EVB. But can't see any message on my
monitor and serial port both.<br>
<br>
<br>
<b>Why did not display any message? </b><b><br>
</b><b>A</b><b>nd could you support correct
configuration file for my EVB?</b><br>
<br>
Thank you. <br>
<br>
<br>
<br>
<br>
<br>
<br>
</font> </div>
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</blockquote>
<br>
</div>
</div>
</div>
<br>
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</blockquote>
</div>
<br>
</div>
</blockquote>
<p><br>
</p>
</div></div></div>
</blockquote></div><br></div>