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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Zoran,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Thanks for the quick reply. I managed to find FITC form a non-intel site and am playing with it.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">For my vendor supplied current image (loaded as a bin) PCIe is enabled (false).<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Images I created with FITC currently do not enter load and stop at POST 0x92. I will play with a bit more to try and get my image back to starting into ramstage
(where it currently crashes).<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Regards,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Naveed.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> coreboot [mailto:coreboot-bounces@coreboot.org]
<b>On Behalf Of </b>Zoran Stojsavljevic<br>
<b>Sent:</b> Tuesday, 17 May 2016 6:21 PM<br>
<b>To:</b> Kathappan E; naveed.ghori@dti.com<br>
<b>Cc:</b> Zeh, Werner; coreboot<br>
<b>Subject:</b> Re: [coreboot] coreboot with fsp hangs at post code 19 on Bayley Bay<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Hello Kathappan, Naveed (I am lazy to reply to separate @s),<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">[1/2] I'll answer these two topics altogether. YES, I am asking for that. It is after all E3825, and this SKU has<o:p></o:p></p>
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<p class="MsoNormal"> significant difference comparing to E3826, E3827 (not sure about this one), and E3845. All of them are<o:p></o:p></p>
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<p class="MsoNormal"> dual-channel DDR3, while E3825 is SINGLE-channel one. YES, YES, you have correct setup, which is<o:p></o:p></p>
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<p class="MsoNormal"> NOT at all important for this topic (sorry, I had to ask you before... Maneuvering in The Dark).<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">[3] Here is The IMPORTANT for you: t<span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#444444">he mentioned PCIe settings are not a part of FSP but rather part of</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#444444"> the descriptor. In the descriptor, soft straps are configured and loaded into the hardware upon reset</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#444444"> release. The strapping can be modified using FITC tool, which is used to configure the flash image and</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#444444"> ME/TXE. If PCIe lanes are disabled in descriptor, Coreboot per default can’t see these PCIe ports.</span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#444444"> You have to modify the descriptor using Flash Image Configuration Tool (FITC) distributed with the TXE</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#444444"> package for Bay Trail.</span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#444444"> <img width="473" height="230" id="_x0000_i1025" src="cid:image001.png@01D1B110.23D9BB80" alt="Inline image 1"></span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#444444">Werner,</span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#444444">I would like to thank you you for enlightening me (I remembered/recalled our private discussion once upon a time about this topic)... I do need to do further
analyses/actions, and teach one seldom old dog (me) the new tricks (they/general public by default say the opposite). ;-)</span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#444444">I sincere hope this @ helps to both of you (TO: list - K and N), and NOT only.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#444444">Zoran</span><o:p></o:p></p>
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<p class="MsoNormal">_______<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Tue, May 17, 2016 at 10:49 AM, Kathappan E <<a href="mailto:Kathappan.E@lnttechservices.com" target="_blank">Kathappan.E@lnttechservices.com</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Hi Zoran,</span><span lang="EN-IN"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><span lang="EN-IN"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Sorry for the late reply since I had a long week end here. Thanks for your comments.</span><span lang="EN-IN"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><span lang="EN-IN"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">[1] Which BYT SoC you are using (example BYT-M N2807)?<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Bayley Bay custom board (not a CRB) which is based Atom
<b>E3825</b> and D0 stepping SoC. But I am not sure whether you are asking this. </span>
<span lang="EN-IN"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">[2] How many DDR3 channels (1 or 2) are you using in your design, and what is the size of memory (most likely not a problem)?<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Single channel non-ECC 1333/1066 MHz soldered DDR3L memory up to 4GB. DIMM0 is populated
with 2 GB and DIMM1 is disabled </span><span lang="EN-IN"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">[3] PCH. Do you have PCIe channels initialized/set in default soft straps (you must have some, at least PCIe root port 0, and PCIe root port 1, as I recalled)?
<<==== IMPORTANT?<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">I didn’t see any PCIe related settings available in bsf file(attached) to edit it. Can
you please help me more on it to change ?</span><span lang="EN-IN"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><i><span lang="EN-IN" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">3 PCIe x1 Gen2 port (0 - 2) , 1 PCIe x1 Gen2 port 3 - GBE</span></i><span lang="EN-IN"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><span lang="EN-IN"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Thanks,</span><span lang="EN-IN"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Kathappan
</span><span lang="EN-IN"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> Zoran Stojsavljevic [mailto:<a href="mailto:zoran.stojsavljevic@gmail.com" target="_blank">zoran.stojsavljevic@gmail.com</a>]
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<b>Sent:</b> 17 May 2016 09:16<br>
<b>To:</b> Kathappan E <<a href="mailto:Kathappan.E@LntTechservices.com">Kathappan.E@LntTechservices.com</a>>; coreboot <<a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a>><br>
<b>Subject:</b> Re: [coreboot] coreboot with fsp hangs at post code 19 on Bayley Bay</span><span lang="EN-IN"><o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Hello Kathappan,<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Did you try to (using BCT) to enable PCIe x1, at least PCIe0 and PCIe1 (the same size x1)? Does it work now?<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Thank you,<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Zoran<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">On Fri, May 13, 2016 at 9:51 PM, Zoran Stojsavljevic <<a href="mailto:zoran.stojsavljevic@gmail.com" target="_blank">zoran.stojsavljevic@gmail.com</a>> wrote:<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Hello Kathappan,<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">I need to look deeper into this area since I am not expert on FSP, but I have some ideas what could be wrong.<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Several questions for you:<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">[1] Which BYT SoC you are using (example BYT-M N2807)?<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">[2] How many DDR3 channels (1 or 2) are you using in your design, and what is the size of memory (most likely not a problem)?<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">[3] PCH. Do you have PCIe channels initialized/set in default soft straps (you must have some, at least PCIe root port 0, and PCIe root port 1, as I recalled)?
<<==== IMPORTANT?<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Again, I need to think more about this, and I'll try to find some answers, later... Please, try to see/discover [3] using BCT tool!<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Zoran<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">_______<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">On Fri, May 13, 2016 at 3:01 PM, Kathappan E <<a href="mailto:Kathappan.E@lnttechservices.com" target="_blank">Kathappan.E@lnttechservices.com</a>> wrote:<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Hi all,<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">When I try coreboot on Bayley Bay platform along with fsp (BAYTRAIL_FSP_GOLD_004_22-MAY-2015), it is getting hang at post code 19.
<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Also I tried with debug version fsp (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG) , it still at that point and below is the debug log.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><b><span lang="EN-IN">Firmware Image</span></b><span lang="EN-IN">: Have used the 8 MB vendor bios and flashed the last 2 MB region(600000 to 7fffff) with coreboot image.
<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><b><span lang="EN-IN">From the debug log</span></b><span lang="EN-IN">: coreboot gives the control to FSP binary routine(<b>FspInitApi</b>) and it is getting hang when trying to
do PCH initialize(<b>PchMiscInit</b>) inside FSP part code. <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><b><span lang="EN-IN">POST 19 code info</span></b><span lang="EN-IN">:
<i>EFI_COMPUTING_UNIT_CHIPSET</i> | <i>EFI_CU_CLOCK_PEI_INIT_ENTRY</i> ==> Clock Init PEIM Entry<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">I have not seen the clock related setting available when customizing fsp binary using BCT.
<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">I tried to disable south cluster component such as EMMC,HSUART,SATA and SIO using BCT , it didn't help me.
<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Can anyone please help me provide some inputs such as related below to proceed further debugging on it ?<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">1. Any other setting we can try out using BCT<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">2. About devices configuration to be initialized byPchMiscInit function.
<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">3. Anything need to be cared/double checked from coreboot side in order to giving control to FspInitApi function.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">4. Does pch straps settings may cause this since I am using upper 6 MB region flash data which is from vendor bios.
<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">4. Please suggest anything on it.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Thanks in advance,<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Kathappan<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"><<<<<<<<<<<< Debug log Start >>>>>>>>>>>>>>><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">coreboot-coreboot-unknown Thu May 12 08:04:42 UTC 2016 romstage starting...<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">RTC Init<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">POST: 0x44<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">POST: 0x47<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">POST: 0x48<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Starting the Intel FSP (early_init)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PM1_STS = 0x0 PM1_CNT = 0x0 GEN_PMCON1 = 0x44000<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">prev_sleep_state = S5<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Configure Default UPD Data<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdMrcInitSPDAddr1: 0xa0 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdMrcInitSPDAddr2: 0xa2 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdSataMode: 0x01 (set)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdLpssSioEnablePciMode: 0x01 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdMrcInitMmioSize: 0x800 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdIgdDvmt50PreAlloc: 0x02 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdApertureSize: 0x02 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdGttSize: 0x02 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">SerialDebugPortAddress: 0x3f8 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">SerialDebugPortType: 0x01 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdMrcDebugMsg: 0x01 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdSccEnablePciMode: 0x01 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">IgdRenderStandby: 0x00 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">TxeUmaEnable: 0x00 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdOsSelection: 0x04 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdEMMC45DDR50Enabled: 0x01 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdEMMC45HS200Enabled: 0x00 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdEMMC45RetuneTimerValue: 0x08 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdEnableIgd: 0x01 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">AutoSelfRefreshEnable: 0x00 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">APTaskTimeoutCnt: 0x00 (default)<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">GTT Size: 2 MB<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Tseg Size: 8 MB<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Aperture Size: 256 MB<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">IGD Memory Size: 64 MB<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">MMIO Size: 2048 MB<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">MIPI/ISP: Disabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Sdio: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Sdcard: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">SATA: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">SIO Dma 0: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">SIO I2C0: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">SIO I2C1: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">SIO I2C2: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">SIO I2C3: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">SIO I2C4: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">SIO I2C5: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">SIO I2C6: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Azalia: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">SIO Dma1: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Pwm0: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Pwm1: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Hsuart0: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Hsuart1: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Spi: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Lpe: Disabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">eMMC Mode: eMMC 4.5<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">SATA Mode: AHCI<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Xhci: Enabled<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">POST: 0x92<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">============= PEIM FSP (VLYVIEW0 0x00000304) =============<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle is 0x0<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFE0FD4<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">The 1th FV start address is 0x000FFFB0000, size is 0x0002F400, handle is 0xFFFB0000<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: A55D6970-1306-440C-8C72-8F51FAFB2926<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdMrcInitTsegSize = 8<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdMrcInitMmioSize = 800<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdMrcInitSPDAddr1 = A0<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PcdMrcInitSPDAddr2 = A2<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Setting BootMode to 0<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">About to call MrcInit();<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">BayleyBay Platform Type<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">RID = 0x11.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Reg_EFF_DualCH_EN = 0x40030040.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">CurrentMrcData.BootMode = 4<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">C1.D0: SPD not present.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Configuring Memory Start...<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">START_RMT:<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft TxDqRight CmdLeft CmdRight<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">------------------------------------------------------------------------------------------------<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Channel 0 Rank 0 -22 21 -21 19 -25 26 0 0<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">STOP_RMT:<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">CMD module is per channel only and without Rank differentiation<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Configuring Memory End<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">UpperTotalMemory = 0x80000000<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">dBMBOUND = 0x80000000<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">dBMBOUNDHI = 0x80000000<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">dGFXBase = 0x7BE00000<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">dTSegBase = 0x7B000000<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Save MRC params.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Current MRC Data DDR Freq 1<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Current MRC Data Core Freq 1<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Current MRC Data Tcl 7<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Current MRC Data WL 6<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Current MRC Data DDRType 1<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Current MRC Data MMIO Size 800<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Current MRC Data TSeg Size 8<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Channel 0<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> Enabled 1<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> Socket 0<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> DimmPresent 1<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> DimmDataWidth 1<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> DimmBusWidth 3<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> DimmSize 2<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> DimmSides 0<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Channel 1<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> Enabled 0<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> Socket 0<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> DimmPresent 0<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> DimmDataWidth 0<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> DimmBusWidth 0<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> DimmSize 0<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> DimmSides 0<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Current MRC Timing Data MRC_DATA_TRP 7<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Current MRC Timing Data MRC_DATA_TRCD 7<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Current MRC Timing Data MRC_DATA_TRAS 13<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Current MRC Timing Data MRC_DATA_TWR 8<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Current MRC Timing Data MRC_DATA_TWTR 4<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Current MRC Timing Data MRC_DATA_TRRD 4<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Current MRC Timing Data MRC_DATA_TRTP 4<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Current MRC Timing Data MRC_DATA_TFAW 1B<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PeiInstallPeiMemory MemoryBegin 0x7AE00000, MemoryLength 0x200000<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Old Stack size 24576, New stack size 131072<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Heap Offset = 0x0 Stack Offset = 0x840F0000<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Stack Hob: BaseAddress=0x7AE00000 Length=0x20000<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFFC1281<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: EF398D58-9DFD-4103-BF94-78C6F4FE712F<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">InstallVlvInitPpi() - Start<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Register PPI Notify: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">InstallVlvInitPpi() - End<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">InstallPchInitPpi() - Start<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PmcBase needs to be programmed and enabled before here.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">ProgramGpioSCForSDCardWA Done....<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Register PPI Notify: 15344673-D365-4BE2-8513-1497CC07611D<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Register PPI Notify: 00B710BA-8CD6-4BF3-AB7A-9A24F54CC334<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 7AFCB3C4<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PchModPhyProgramming() - Start<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">SOC B0 and later ModPhy Table programming<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PchModPhyProgramming() - End<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PchSataInit() - Start<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PchSataInit() - End<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">InstallPchInitPpi() - End<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Register PPI Notify: 5BAB88BA-E0E2-4674-B6AD-B812F6881CD6<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Register PPI Notify: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: DD29124D-7819-4F15-BB07-351E7451D71C<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Notify: PPI Guid: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3, Peim notify entry point: 7AFDE2E9<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">VlvInitPeiEntryPoint start....<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">------------------------ VLV SSA Platform Policy dump Begin ---------------<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Graphics Configuration:<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">GttSize : 2 MB<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">IgdDvmt50PreAlloc : 2<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PrimaryDisplay : 0<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">ApertureSize : 2<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Turbo Enable : 1<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">------------------------ VLV SSA Platform Policy dump END -----------------<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">ProgramEcBase Done....<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">SSASafeConfiguration Done....<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Clear Dbuff to all zero before read 0xFFFFFFFF<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PUNIT_ISPSSPM0 value is 0x3000003<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">ISP Device is enabled by fuse<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Skip ISPConfig<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">InitThermalRegisters Done....<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">IGD enabled.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">IGD Turbo Enable.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PUNIT_BIOS_CONFIG11 = 0x400301C0.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PUNIT_BIOS_CONFIG22 = 0x40030140.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">TotalMmioLength: 0x10400000 bytes<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">GraphicsInit Done....<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: 09EA8911-BE0D-4230-A003-EDC693B48E11<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install mVlvPeiInitPpi Done....<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Install PPI: 15344673-D365-4BE2-8513-1497CC07611D<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">Notify: PPI Guid: 15344673-D365-4BE2-8513-1497CC07611D, Peim notify entry point: 7AFCBB94<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PchInitialize() - Start<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN">PchMiscInit() - Start<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"><<<<<<<<<<<<<<<<<< Debug log Start end >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><o:p></o:p></span></p>
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<p><strong><span lang="EN-IN">L&T Technology Services Ltd</span></strong><span lang="EN-IN"><o:p></o:p></span></p>
<p><span lang="EN-IN"><a href="http://www.lnttechservices.com/" target="_blank">www.LntTechservices.com</a><o:p></o:p></span></p>
<p><span lang="EN-IN">This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN" style="color:#888888">--<br>
coreboot mailing list: <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br>
<a href="https://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">https://www.coreboot.org/mailman/listinfo/coreboot</a></span><span lang="EN-IN"><o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-IN"> <o:p></o:p></span></p>
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<p><strong><span lang="EN-IN">L&T Technology Services Ltd</span></strong><span lang="EN-IN"><o:p></o:p></span></p>
<p><span lang="EN-IN"><a href="http://www.lnttechservices.com/" target="_blank">www.LntTechservices.com</a><o:p></o:p></span></p>
<p><span lang="EN-IN">This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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