<div dir="ltr">YuSeok,<div><br></div><div>It looks your platform has enabled the Memory Down function.</div><div><br></div><div>The MEM_DOWN_DIMM_SPD_DATA structure supposed to be filled with the relative DIMM SPD data as described in comments, for example,</div><div><br></div><div><blockquote type="cite" style="font-size:12.8px"><font face="굴림체">DRAMDeviceType =>>> SPD Byte Offset 2<br></font><span style="font-family:굴림체;font-size:small">ModuleType =>>> SPD Byte offset 3<br></span><span style="font-size:small">DramManufacturerIdLsb =>>> SPD Byte offset 148</span><font face="굴림체"><br></font></blockquote></div><div><br></div><div>To have a look at below links to understand the DDR3's SPD details.</div><div><br></div><div><a href="http://www.simmtester.com/page/news/showpubnews.asp?num=153">http://www.simmtester.com/page/news/showpubnews.asp?num=153</a><br></div><div><br></div><div><a href="https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=3&cad=rja&uact=8&ved=0ahUKEwiMxt_PzrfNAhVQF8AKHQfkAJ8QFgg3MAI&url=https%3A%2F%2Fwww.micron.com%2F~%2Fmedia%2Fdocuments%2Fproducts%2Ftechnical-note%2Fdram-modules%2Ftn_04_42.pdf&usg=AFQjCNEBeya4qkEodTkCc1eEjuK5Qdz0YA&sig2=S9r0YXabVNhpO_UfzJqNpQ&bvm=bv.125221236,d.ZGg">https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=3&cad=rja&uact=8&ved=0ahUKEwiMxt_PzrfNAhVQF8AKHQfkAJ8QFgg3MAI&url=https%3A%2F%2Fwww.micron.com%2F~%2Fmedia%2Fdocuments%2Fproducts%2Ftechnical-note%2Fdram-modules%2Ftn_04_42.pdf&usg=AFQjCNEBeya4qkEodTkCc1eEjuK5Qdz0YA&sig2=S9r0YXabVNhpO_UfzJqNpQ&bvm=bv.125221236,d.ZGg</a><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jun 1, 2016 at 7:53 AM, 김유석 <span dir="ltr"><<a href="mailto:poplinux0@gmail.com" target="_blank">poplinux0@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div bgcolor="#FFFFFF" text="#000000">
<font face="굴림체">Dear Sir.</font>
<p><font face="굴림체">My own product must need a change the
value(config) of sdram. Such as size, speed, and etc.<br>
</font></p>
<p><font face="굴림체"><br>
</font></p>
<p><font face="굴림체">So, I'm try to search and study the coreboot
source code, and found out the
"vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h"</font></p>
<p><font face="굴림체"><br>
</font></p>
<p><font face="굴림체">This header are contained the some structure for
setup the sdram. such as "MEM_DOWN_DIMM_SPD_DATA;"</font></p>
<p><font face="굴림체"><br>
</font></p>
<p><font face="굴림체">
</font></p><blockquote type="cite"><font face="굴림체"> 50 typedef struct {<br>
51 UINT8 DRAMDeviceType; // 2 DRAM
Device Type<br>
52 UINT8 ModuleType; // 3 Module
Type<br>
53 UINT8 SDRAMDensityAndBanks; // 4 SDRAM
Density and Banks<br>
54 UINT8 SDRAMAddressing; // 5 SDRAM
Addressing<br>
55 UINT8 VDD; // 6 Module
Nominal Voltage<br>
56 UINT8 ModuleOrganization; // 7 Module
Organization<br>
57 UINT8 ModuleMemoryBusWidth; </font></blockquote><font face="굴림체">
<blockquote type="cite"> 94 UINT8
DramManufacturerIdLsb; // 148 DRAM Manufacturer ID
Code, LSB<br>
95 UINT8 DramManufacturerIdMsb; // 149 DRAM
Manufacturer ID Code, MSB<br>
96 } MEM_DOWN_DIMM_SPD_DATA;<br>
</blockquote>
<br>
</font><p></p>
<p><font face="굴림체"><br>
</font></p>
<p><font face="굴림체">So, I'm try to found <b>*.c</b> source codes
for check configuration point.</font></p>
<p><font face="굴림체">But, coreboot are not setup the argument of
sdram.</font></p>
<br>
<font face="굴림체">I don't understand this sisution, Because sdram is
must need a some configuration for use.<br>
<br>
<br>
<b>Why? do not setup the argument of sd</b><b>ram ???<br>
<br>
</b><b></b><br>
Please advise to me.<br>
<br>
Thank you.<br>
<br>
<br>
<br>
</font>
</div>
<br>--<br>
coreboot mailing list: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
<a href="https://www.coreboot.org/mailman/listinfo/coreboot" rel="noreferrer" target="_blank">https://www.coreboot.org/mailman/listinfo/coreboot</a><br></blockquote></div><br></div>