<div dir="ltr">INCLUDE_ME & ME_PATH was used before, but it has changed to IFD_BIN_PATH recently. Did you define IFD_BIN_PATH with path/descriptor.bin? It should work!</div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jun 21, 2016 at 2:16 AM, 김유석 <span dir="ltr"><<a href="mailto:poplinux0@gmail.com" target="_blank">poplinux0@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div bgcolor="#FFFFFF" text="#000000">
<div>Dear Sir.<br>
<br>
Thank's your prompt reply.<br>
<br>
My coreboot source code download from coreboot GIT and ADI's
coreboot GIT. both.<br>
<br>
This time, I work on official coreboot GIT(not ADI's GIT, but i
can do ADI's GIT)<br>
<br>
<br>
<br>
<b>- attach the descriptor.bin<br>
<br>
</b> I was select the <font color="#ff0000">"CONFIG_HAVE_IFD_BIN",
"CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY"</font>, and fill-up the
<font color="#ff0000">"CONFIG_IFD_BIN_PATH".</font><br>
And descriptor.bin is extract from ADI's EVB.<br>
<br>
<b> 131 CONFIG_HAVE_IFD_BIN=y</b><br>
308 #<br>
309 # Southbridge<br>
310 #<br>
311 # CONFIG_AMD_SB_CIMX is not set<br>
312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set<br>
313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set<br>
314 CONFIG_SOUTH_BRIDGE_OPTIONS=y<br>
315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set<br>
316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set<br>
<b> 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y</b><b><br>
</b><b> 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"</b><br>
<br>
<img alt="" src="cid:part1.2FBA829C.085C160D@gmail.com" height="912" width="943"><br>
<br>
<br>
<br>
<br>
<b>- Not exist "INCLUDE_ME" and "ME_PATH"</b><br>
<br>
I'm can't setup the "INCLUDE_ME" and "ME_PATH" Because thie
keyword is not exist coreboot's source tree.<br>
<br>
I was try to find the "INCLUDE_ME" and "ME_PATH" from coreboot
source, But not exist this keyword.<br>
<br>
<b>poplinux@raw coreboot $ > ls</b><br>
3rdparty Documentation Makefile README cscope.out src
toolchain.inc<br>
COPYING MAINTAINERS Makefile.inc build payloads tags
util<br>
<br>
<b>poplinux@raw coreboot $ > grep "INCLUDE_ME" * -Rn</b><br>
<br>
<b>poplinux@raw coreboot $ > grep "ME_PATH" * -Rn</b><br>
cscope.out:9055111:CONFIG_RESUME_PATH_SAME_AS_BOOT<br>
cscope.out:16228575:CONFIG_RESUME_PATH_SAME_AS_BOOT<br>
cscope.out:16229157:CONFIG_RESUME_PATH_SAME_AS_BOOT<br>
src/cscope.out:354905:CONFIG_RESUME_PATH_SAME_AS_BOOT<br>
src/cscope.out:7528183:CONFIG_RESUME_PATH_SAME_AS_BOOT<br>
src/cscope.out:7528765:CONFIG_RESUME_PATH_SAME_AS_BOOT<br>
src/vendorcode/google/chromeos/vboot2/vboot_logic.c:125: if
(!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT))<br>
src/vendorcode/google/chromeos/vboot2/vboot_logic.c:311: if
(IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) &&<br>
src/drivers/intel/fsp1_1/romstage.c:181:
!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) &&<br>
src/Kconfig:540:config RESUME_PATH_SAME_AS_BOOT<span class=""><br>
<br>
<br>
Please advise to me.<br>
<br>
Thank you.<br>
<br>
<br>
<br>
<br></span>
2016-06-21 오전 6:58에 WANG FEI 이(가) 쓴 글:<br>
</div><div><div class="h5">
<blockquote type="cite">
<div dir="ltr">Here is a sample,
<div><br>
</div>
<div>Please select INCLUDE_ME to y and set ME_PATH to point to
your descriptor.bin (Path/descriptor.bin, refer to FSP_FILE as
a sample).</div>
</div>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Mon, Jun 20, 2016 at 10:48 PM, WANG
FEI <span dir="ltr"><<a href="mailto:wangfei.jimei@gmail.com" target="_blank">wangfei.jimei@gmail.com</a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div dir="ltr">YuSeok, how did you attach the descriptor.bin
to your coreboot? Did you follow the previous mail to
include descriptor.bin with <span style="color:rgb(0,0,0);white-space:pre-wrap">INCLUDE_ME and ME_PATH in .config?</span></div>
<div class="gmail_extra"><br>
<div class="gmail_quote">
<div>
<div>On Mon, Jun 20, 2016 at 6:46 AM, 김유석 <span dir="ltr"><<a href="mailto:poplinux0@gmail.com" target="_blank">poplinux0@gmail.com</a>></span>
wrote:<br>
</div>
</div>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div>
<div>
<div bgcolor="#FFFFFF" text="#000000"> <font face="굴림체">Dear Sir.</font>
<p><font face="굴림체"><br>
My ENV</font></p>
<p><font face="굴림체"> EVB : ADI SG-2440</font></p>
<p><font face="굴림체"> source : official coreboot</font></p>
<p><font face="굴림체"> FSP : intel FSP 4.0</font></p>
<p><font face="굴림체"> <br>
</font></p>
<p><font face="굴림체">I was successfully build-up
the coreboot and successfully boot-up my
EVB.</font></p>
<p><font face="굴림체"><br>
</font></p>
<p><font face="굴림체">But My EVB's GbE is not
activated(not running.)</font></p>
<p><font face="굴림체"><br>
</font></p>
<p><font face="굴림체">So, I was try to boot using
the original OEM bios(from ADI). <b>This
image is </b><b>act</b><b>vate the GbE</b>.</font></p>
<p><font face="굴림체"><br>
</font></p>
<p><font face="굴림체">Another developer was same
quetion to Coreboot communite. And He is
resolved this issue.<br>
</font></p>
<p><font face="굴림체"><a href="https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html" target="_blank">https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html</a><br>
</font></p>
<p><font face="굴림체"><br>
</font></p>
<p><font face="굴림체">This guy's said that "Must
add the descriptor.bin to coreboot.bin".</font></p>
<p><font face="굴림체"><br>
</font></p>
<p><font face="굴림체">So, I was extract the
descriptor.bin from ADI's coreboot.bin <br>
</font></p>
<p><font face="굴림체">And successfully attached
the descriptor.bin to my coreboot.bin.</font></p>
<p><font face="굴림체"> <b>oem_dumped.bin =>
ADI's default </b><b>coreboot.bin, This
image are activated the GbE.</b><br>
</font></p>
<p><font face="굴림체"> <b>poplinux@raw bins $
></b> ./ifdtool -x src/oem_dumped.bin <br>
File src/oem_dumped.bin is 8388608 bytes <br>
Flash Region 0 (Flash Descriptor):
00000000 - 0000ffff <br>
Flash Region 1 (BIOS): 00010000 -
007fffff <br>
Flash Region 2 (Intel ME): 00fff000 -
00000fff (unused)<br>
Flash Region 3 (GbE): 00fff000 -
00000fff (unused)<br>
Flash Region 4 (Platform Data): 00fff000
- 00000fff (unused)</font></p>
<p><font face="굴림체"> <b>poplinux@raw bins $
></b> ln -s
./flashregion_0_flashdescriptor.bin
descriptor.bin<br>
<b>poplinux@raw bins $ ></b> ./ifdtool
-d ./descriptor.bin <br>
File ./descriptor.bin is 65536 bytes<br>
FLMAP0: 0x01040003<br>
NR: 1<br>
FRBA: 0x40<br>
NC: 1<br>
FCBA: 0x30<br>
FLMAP1: 0x09100206<br>
ISL: 0x09<br>
FPSBA: 0x100<br>
NM: 2<br>
FMBA: 0x60<br>
FLMAP2: 0x00210020<br>
PSL: 0x2100<br>
FMSBA: 0x200<br>
FLUMAP1: 0x000002e0<br>
Intel ME VSCC Table Length (VTL):
2<br>
Intel ME VSCC Table Base Address (VTBA):
0x000e00<br>
<br>
ME VSCC table:<br>
JID0: 0x001740ef<br>
SPI Componend Device ID 1:
0x17<br>
SPI Componend Device ID 0:
0x40<br>
SPI Componend Vendor ID:
0xef<br>
VSCC0: 0x20052005<br>
Lower Erase Opcode:
0x20<br>
Lower Write Enable on Write Status:
0x50<br>
Lower Write Status Required: No<br>
Lower Write Granularity: 64
bytes<br>
Lower Block / Sector Erase Size:
4KB<br>
Upper Erase Opcode:
0x20<br>
Upper Write Enable on Write Status:
0x50<br>
Upper Write Status Required: No<br>
Upper Write Granularity: 64
bytes<br>
Upper Block / Sector Erase Size:
4KB<br>
<br>
OEM Section:<br>
00: 31 31 35 32 31 35 30 39 32 30 00 00 00
00 00 00<br>
10: 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00<br>
20: 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00<br>
30: 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00<br>
<br>
Found Region Section<br>
FLREG0: 0x000f0000<br>
Flash Region 0 (Flash Descriptor):
00000000 - 0000ffff <br>
FLREG1: 0x07ff0010<br>
Flash Region 1 (BIOS): 00010000 -
007fffff <br>
FLREG2: 0x00000fff<br>
Flash Region 2 (Intel ME): 00fff000 -
00000fff (unused)<br>
FLREG3: 0x00000fff<br>
Flash Region 3 (GbE): 00fff000 -
00000fff (unused)<br>
FLREG4: 0x00000fff<br>
Flash Region 4 (Platform Data): 00fff000
- 00000fff (unused)<br>
<br>
Found Component Section<br>
FLCOMP 0x09200024<br>
Dual Output Fast Read Support: not
supported<br>
Read ID/Read Status Clock Frequency:
33MHz<br>
Write/Erase Clock Frequency:
33MHz<br>
Fast Read Clock Frequency:
33MHz<br>
Fast Read Support: not
supported<br>
Read Clock Frequency:
20MHz<br>
Component 2 Density: 8MB<br>
Component 1 Density: 8MB<br>
FLILL 0x00000000<br>
Invalid Instruction 3: 0x00<br>
Invalid Instruction 2: 0x00<br>
Invalid Instruction 1: 0x00<br>
Invalid Instruction 0: 0x00<br>
FLPB 0x00000000<br>
Flash Partition Boundary Address:
0x000000<br>
<br>
Found PCH Strap Section<br>
PCHSTRP0: 0x00080002<br>
PCHSTRP1: 0x00000000<br>
PCHSTRP2: 0x00000000<br>
PCHSTRP3: 0x00000003<br>
PCHSTRP4: 0x0000007f<br>
PCHSTRP5: 0x007fffc0<br>
PCHSTRP6: 0x0001c7c0<br>
PCHSTRP7: 0x00000624<br>
PCHSTRP8: 0x00000000<br>
PCHSTRP9: 0xffffffff<br>
PCHSTRP10: 0xffffffff<br>
PCHSTRP11: 0xffffffff<br>
PCHSTRP12: 0xffffffff<br>
PCHSTRP13: 0xffffffff<br>
PCHSTRP14: 0xffffffff<br>
PCHSTRP15: 0xffffffff<br>
PCHSTRP16: 0xffffffff<br>
PCHSTRP17: 0xffffffff<br>
<br>
Found Master Section<br>
FLMSTR1: 0x1f1f0000 (Host CPU/BIOS)<br>
Platform Data Region Write Access:
enabled<br>
GbE Region Write Access:
enabled<br>
Intel ME Region Write Access:
enabled<br>
Host CPU/BIOS Region Write Access:
enabled<br>
Flash Descriptor Write Access:
enabled<br>
Platform Data Region Read Access:
enabled<br>
GbE Region Read Access:
enabled<br>
Intel ME Region Read Access:
enabled<br>
Host CPU/BIOS Region Read Access:
enabled<br>
Flash Descriptor Read Access:
enabled<br>
Requester ID:
0x0000<br>
<br>
FLMSTR2: 0x08090118 (Intel ME)<br>
Platform Data Region Write Access:
disabled<br>
GbE Region Write Access:
enabled<br>
Intel ME Region Write Access:
disabled<br>
Host CPU/BIOS Region Write Access:
disabled<br>
Flash Descriptor Write Access:
disabled<br>
Platform Data Region Read Access:
disabled<br>
GbE Region Read Access:
enabled<br>
Intel ME Region Read Access:
disabled<br>
Host CPU/BIOS Region Read Access:
disabled<br>
Flash Descriptor Read Access:
enabled<br>
Requester ID:
0x0118<br>
<br>
FLMSTR3: 0xffffffff (GbE)<br>
Platform Data Region Write Access:
enabled<br>
GbE Region Write Access:
enabled<br>
Intel ME Region Write Access:
enabled<br>
Host CPU/BIOS Region Write Access:
enabled<br>
Flash Descriptor Write Access:
enabled<br>
Platform Data Region Read Access:
enabled<br>
GbE Region Read Access:
enabled<br>
Intel ME Region Read Access:
enabled<br>
Host CPU/BIOS Region Read Access:
enabled<br>
Flash Descriptor Read Access:
enabled<br>
Requester ID:
0xffff<br>
<br>
Found Processor Strap Section<br>
????: 0xffffffff<br>
????: 0xffffffff<br>
????: 0xffffffff<br>
????: 0xffffffff<br>
</font></p>
<p><br>
</p>
<p><font face="굴림체">But GbE is still
de-activated. boot log is see below.</font></p>
<p><font face="굴림체"><br>
</font></p>
<p><font face="굴림체"> PCI: pci_scan_bus for bus
00<br>
PCI: 00:00.0 [8086/0000] ops<br>
PCI: 00:00.0 [8086/1f0e] enabled<br>
Capability: type 0x10 @ 0x40<br>
Capability: type 0x01 @ 0x80<br>
Capability: type 0x0d @ 0x88<br>
Capability: type 0x05 @ 0x90<br>
Capability: type 0x10 @ 0x40<br>
PCI: 00:01.0 subordinate bus PCI Express<br>
PCI: 00:01.0 [8086/1f10] enabled<br>
PCI: Static device PCI: 00:02.0 not found,
disabling it.<br>
Capability: type 0x10 @ 0x40<br>
Capability: type 0x01 @ 0x80<br>
Capability: type 0x0d @ 0x88<br>
Capability: type 0x05 @ 0x90<br>
Capability: type 0x10 @ 0x40<br>
PCI: 00:03.0 subordinate bus PCI Express<br>
PCI: 00:03.0 [8086/1f12] enabled<br>
PCI: Static device PCI: 00:04.0 not found,
disabling it.<br>
PCI: 00:0b.0 [8086/1f18] enabled<br>
PCI: 00:0e.0 [8086/1f14] enabled<br>
PCI: 00:0f.0 [8086/1f16] enabled<br>
PCI: 00:13.0 [8086/1f15] enabled<br>
<font color="#ff0000"><b> PCI: Static
device PCI: 00:14.0 not found, disabling
it.</b><b><br>
</b><b> PCI: Static device PCI: 00:14.1
not found, disabling it.</b><b><br>
</b><b> PCI: Static device PCI: 00:14.2
not found, disabling it.</b><b><br>
</b><b> PCI: Static device PCI: 00:14.3
not found, disabling it</b></font>.<br>
</font></p>
<p><font face="굴림체"><br>
</font></p>
<p><font face="굴림체">I don't have a any idea for
activate the GbE.</font></p>
<p><font face="굴림체"><br>
</font></p>
<p><font face="굴림체">Please advise to me.</font></p>
<p><font face="굴림체">Thank you. </font><br>
</p>
<p><font face="굴림체"><br>
</font></p>
<p><font face="굴림체"><br>
</font></p>
<p><font face="굴림체"><br>
</font></p>
</div>
<br>
</div>
</div>
<span><font color="#888888">--<br>
coreboot mailing list: <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br>
<a href="https://www.coreboot.org/mailman/listinfo/coreboot" rel="noreferrer" target="_blank">https://www.coreboot.org/mailman/listinfo/coreboot</a><br>
</font></span></blockquote>
</div>
<br>
</div>
</blockquote>
</div>
<br>
</div>
</blockquote>
<p><br>
</p>
</div></div></div>
</blockquote></div><br></div>