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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Hi,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">You are using the Intel Rangeley FSP 4.0 release.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">I assume that you downloaded this from
<a href="http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html">
http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html</a>
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">With this download you should have received the supporting documentation, including the FSP Integration Guide.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Also included in the download you should have received the RangeleyFsp.bsf file.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">This BSF file can be used with the Intel BCT, also available on
<a href="http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html">
http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html</a> , to configure settings in the Intel FSP binary.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Review the FSP Integration Guide for more info regarding the FSP binary configuration settings.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Maybe you have configured the Rangeley FSP binary to disable the GbE devices.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Use the BCT to enable the GbE devices, look for the “Enable LAN” option.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Also, coreboot has the ability to overwrite these settings via the UPD_DATA_REGION structure.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Please search your coreboot for PcdEnableLan, if found make sure this is set to “1”.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Regards,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">David<o:p></o:p></span></p>
<p class="MsoNormal"><a name="_MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></a></p>
<p class="MsoNormal"><a name="_____replyseparator"></a><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> coreboot [mailto:coreboot-bounces@coreboot.org]
<b>On Behalf Of </b>WANG FEI<br>
<b>Sent:</b> Thursday, June 23, 2016 10:16 PM<br>
<b>To:</b> </span><span style="font-size:11.0pt;font-family:"Malgun Gothic",sans-serif">김유석</span><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> <poplinux0@gmail.com><br>
<b>Cc:</b> coreboot <coreboot@coreboot.org><br>
<b>Subject:</b> Re: [coreboot] The GbE is not activated on my Board.<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<p class="MsoNormal">Can you send me the descriptor.bin and your coreboot image? I can review it.<o:p></o:p></p>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
</div>
<div>
<p class="MsoNormal">BTW, your image is running on Mohon Peak platform, right? I just have one Mohon Peak platform to test.<o:p></o:p></p>
</div>
</div>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<p class="MsoNormal">On Wed, Jun 22, 2016 at 7:37 AM, <span style="font-family:"Calibri",sans-serif">
김유석</span> <<a href="mailto:poplinux0@gmail.com" target="_blank">poplinux0@gmail.com</a>> wrote:<o:p></o:p></p>
<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-right:0in">
<div>
<div>
<p class="MsoNormal">Dear Sir. <br>
<br>
I have already defined the "CONFIG_IFD_BIN_PATH"<br>
<br>
<b> 131 CONFIG_HAVE_IFD_BIN=y</b><br>
308 #<br>
309 # Southbridge<br>
310 #<br>
311 # CONFIG_AMD_SB_CIMX is not set<br>
312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set<br>
313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set<br>
314 CONFIG_SOUTH_BRIDGE_OPTIONS=y<br>
315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set<br>
316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set<br>
<b> 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y<br>
318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"</b><br>
<br>
And successfully add to coreboot.bin<br>
<br>
<br>
poplinux@raw coreboot $ > ./ifdtool -d coreboot.bin <br>
File src/oem_dumped.bin is 8388608 bytes<o:p></o:p></p>
<div>
<div>
<p class="MsoNormal" style="margin-bottom:12.0pt">FLMAP0: 0x01040003<br>
NR: 1<br>
FRBA: 0x40<br>
NC: 1<br>
FCBA: 0x30<br>
FLMAP1: 0x09100206<br>
ISL: 0x09<br>
FPSBA: 0x100<br>
NM: 2<br>
FMBA: 0x60<br>
FLMAP2: 0x00210020<br>
PSL: 0x2100<br>
FMSBA: 0x200<br>
FLUMAP1: 0x000002e0<br>
Intel ME VSCC Table Length (VTL): 2<br>
Intel ME VSCC Table Base Address (VTBA): 0x000e00<br>
<br>
ME VSCC table:<br>
JID0: 0x001740ef<br>
SPI Componend Device ID 1: 0x17<br>
SPI Componend Device ID 0: 0x40<br>
SPI Componend Vendor ID: 0xef<br>
VSCC0: 0x20052005<br>
Lower Erase Opcode: 0x20<br>
Lower Write Enable on Write Status: 0x50<br>
Lower Write Status Required: No<br>
Lower Write Granularity: 64 bytes<br>
Lower Block / Sector Erase Size: 4KB<br>
Upper Erase Opcode: 0x20<br>
Upper Write Enable on Write Status: 0x50<br>
Upper Write Status Required: No<br>
Upper Write Granularity: 64 bytes<br>
Upper Block / Sector Erase Size: 4KB<br>
<br>
OEM Section:<br>
00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00<br>
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
<br>
Found Region Section<br>
FLREG0: 0x000f0000<br>
Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff <br>
FLREG1: 0x07ff0010<br>
Flash Region 1 (BIOS): 00010000 - 007fffff <br>
FLREG2: 0x00000fff<br>
Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused)<br>
FLREG3: 0x00000fff<br>
Flash Region 3 (GbE): 00fff000 - 00000fff (unused)<br>
FLREG4: 0x00000fff<br>
Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)<br>
<br>
Found Component Section<br>
FLCOMP 0x09200024<br>
Dual Output Fast Read Support: not supported<br>
Read ID/Read Status Clock Frequency: 33MHz<br>
Write/Erase Clock Frequency: 33MHz<br>
Fast Read Clock Frequency: 33MHz<br>
Fast Read Support: not supported<br>
Read Clock Frequency: 20MHz<br>
Component 2 Density: 8MB<br>
Component 1 Density: 8MB<br>
FLILL 0x00000000<br>
Invalid Instruction 3: 0x00<br>
Invalid Instruction 2: 0x00<br>
Invalid Instruction 1: 0x00<br>
Invalid Instruction 0: 0x00<br>
FLPB 0x00000000<br>
Flash Partition Boundary Address: 0x000000<br>
<br>
Found PCH Strap Section<br>
PCHSTRP0: 0x00080002<br>
PCHSTRP1: 0x00000000<br>
PCHSTRP2: 0x00000000<br>
PCHSTRP3: 0x00000003<br>
PCHSTRP4: 0x0000007f<br>
PCHSTRP5: 0x007fffc0<br>
PCHSTRP6: 0x0001c7c0<br>
PCHSTRP7: 0x00000624<br>
PCHSTRP8: 0x00000000<br>
PCHSTRP9: 0xffffffff<br>
PCHSTRP10: 0xffffffff<br>
PCHSTRP11: 0xffffffff<br>
PCHSTRP12: 0xffffffff<br>
PCHSTRP13: 0xffffffff<br>
PCHSTRP14: 0xffffffff<br>
PCHSTRP15: 0xffffffff<br>
PCHSTRP16: 0xffffffff<br>
PCHSTRP17: 0xffffffff<br>
<br>
Found Master Section<br>
FLMSTR1: 0x1f1f0000 (Host CPU/BIOS)<br>
Platform Data Region Write Access: enabled<br>
GbE Region Write Access: enabled<br>
Intel ME Region Write Access: enabled<br>
Host CPU/BIOS Region Write Access: enabled<br>
Flash Descriptor Write Access: enabled<br>
Platform Data Region Read Access: enabled<br>
GbE Region Read Access: enabled<br>
Intel ME Region Read Access: enabled<br>
Host CPU/BIOS Region Read Access: enabled<br>
Flash Descriptor Read Access: enabled<br>
Requester ID: 0x0000<br>
<br>
FLMSTR2: 0x08090118 (Intel ME)<br>
Platform Data Region Write Access: disabled<br>
GbE Region Write Access: enabled<br>
Intel ME Region Write Access: disabled<br>
Host CPU/BIOS Region Write Access: disabled<br>
Flash Descriptor Write Access: disabled<br>
Platform Data Region Read Access: disabled<br>
GbE Region Read Access: enabled<br>
Intel ME Region Read Access: disabled<br>
Host CPU/BIOS Region Read Access: disabled<br>
Flash Descriptor Read Access: enabled<br>
Requester ID: 0x0118<br>
<br>
FLMSTR3: 0xffffffff (GbE)<br>
Platform Data Region Write Access: enabled<br>
GbE Region Write Access: enabled<br>
Intel ME Region Write Access: enabled<br>
Host CPU/BIOS Region Write Access: enabled<br>
Flash Descriptor Write Access: enabled<br>
Platform Data Region Read Access: enabled<br>
GbE Region Read Access: enabled<br>
Intel ME Region Read Access: enabled<br>
Host CPU/BIOS Region Read Access: enabled<br>
Flash Descriptor Read Access: enabled<br>
Requester ID: 0xffff<br>
<br>
Found Processor Strap Section<br>
????: 0xffffffff<br>
????: 0xffffffff<br>
????: 0xffffffff<br>
????: 0xffffffff<br>
<br>
<br>
<o:p></o:p></p>
</div>
</div>
<p class="MsoNormal">But, GbE still not running.<br>
<br>
Please advise to me. <br>
<br>
Thank you.<br>
<br>
<br>
<br>
<br>
<br>
<br>
<br>
2016-06-22 <span style="font-family:"Calibri",sans-serif">오전</span> 12:54<span style="font-family:"Calibri",sans-serif">에</span> WANG FEI
<span style="font-family:"Calibri",sans-serif">이</span>(<span style="font-family:"Calibri",sans-serif">가</span>)
<span style="font-family:"Calibri",sans-serif">쓴</span> <span style="font-family:"Calibri",sans-serif">
글</span>:<o:p></o:p></p>
</div>
<div>
<div>
<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
<div>
<p class="MsoNormal">INCLUDE_ME & ME_PATH was used before, but it has changed to IFD_BIN_PATH recently. Did you define IFD_BIN_PATH with path/descriptor.bin? It should work!<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<p class="MsoNormal">On Tue, Jun 21, 2016 at 2:16 AM, <span style="font-family:"Calibri",sans-serif">
김유석</span> <<a href="mailto:poplinux0@gmail.com" target="_blank">poplinux0@gmail.com</a>> wrote:<o:p></o:p></p>
<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-right:0in">
<div>
<div>
<p class="MsoNormal">Dear Sir.<br>
<br>
Thank's your prompt reply.<br>
<br>
My coreboot source code download from coreboot GIT and ADI's coreboot GIT. both.<br>
<br>
This time, I work on official coreboot GIT(not ADI's GIT, but i can do ADI's GIT)<br>
<br>
<br>
<br>
<b>- attach the descriptor.bin<br>
<br>
</b> I was select the <span style="color:red">"CONFIG_HAVE_IFD_BIN", "CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY"</span>, and fill-up the
<span style="color:red">"CONFIG_IFD_BIN_PATH".</span><br>
And descriptor.bin is extract from ADI's EVB.<br>
<br>
<b> 131 CONFIG_HAVE_IFD_BIN=y</b><br>
308 #<br>
309 # Southbridge<br>
310 #<br>
311 # CONFIG_AMD_SB_CIMX is not set<br>
312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set<br>
313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set<br>
314 CONFIG_SOUTH_BRIDGE_OPTIONS=y<br>
315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set<br>
316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set<br>
<b> 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y<br>
318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"</b><br>
<br>
<img border="0" width="943" height="912" id="_x0000_i1025" src="cid:image001.jpg@01D1CEED.67E8B510"><br>
<br>
<br>
<br>
<br>
<b>- Not exist "INCLUDE_ME" and "ME_PATH"</b><br>
<br>
I'm can't setup the "INCLUDE_ME" and "ME_PATH" Because thie keyword is not exist coreboot's source tree.<br>
<br>
I was try to find the "INCLUDE_ME" and "ME_PATH" from coreboot source, But not exist this keyword.<br>
<br>
<b>poplinux@raw coreboot $ > ls</b><br>
3rdparty Documentation Makefile README cscope.out src toolchain.inc<br>
COPYING MAINTAINERS Makefile.inc build payloads tags util<br>
<br>
<b>poplinux@raw coreboot $ > grep "INCLUDE_ME" * -Rn</b><br>
<br>
<b>poplinux@raw coreboot $ > grep "ME_PATH" * -Rn</b><br>
cscope.out:9055111:CONFIG_RESUME_PATH_SAME_AS_BOOT<br>
cscope.out:16228575:CONFIG_RESUME_PATH_SAME_AS_BOOT<br>
cscope.out:16229157:CONFIG_RESUME_PATH_SAME_AS_BOOT<br>
src/cscope.out:354905:CONFIG_RESUME_PATH_SAME_AS_BOOT<br>
src/cscope.out:7528183:CONFIG_RESUME_PATH_SAME_AS_BOOT<br>
src/cscope.out:7528765:CONFIG_RESUME_PATH_SAME_AS_BOOT<br>
src/vendorcode/google/chromeos/vboot2/vboot_logic.c:125: if (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT))<br>
src/vendorcode/google/chromeos/vboot2/vboot_logic.c:311: if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) &&<br>
src/drivers/intel/fsp1_1/romstage.c:181: !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) &&<br>
src/Kconfig:540:config RESUME_PATH_SAME_AS_BOOT<br>
<br>
<br>
Please advise to me.<br>
<br>
Thank you.<br>
<br>
<br>
<br>
<br>
2016-06-21 <span style="font-family:"Calibri",sans-serif">오전</span> 6:58<span style="font-family:"Calibri",sans-serif">에</span> WANG FEI
<span style="font-family:"Calibri",sans-serif">이</span>(<span style="font-family:"Calibri",sans-serif">가</span>)
<span style="font-family:"Calibri",sans-serif">쓴</span> <span style="font-family:"Calibri",sans-serif">
글</span>:<o:p></o:p></p>
</div>
<div>
<div>
<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
<div>
<p class="MsoNormal">Here is a sample, <o:p></o:p></p>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
</div>
<div>
<p class="MsoNormal">Please select INCLUDE_ME to y and set ME_PATH to point to your descriptor.bin (Path/descriptor.bin, refer to FSP_FILE as a sample).<o:p></o:p></p>
</div>
</div>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<p class="MsoNormal">On Mon, Jun 20, 2016 at 10:48 PM, WANG FEI <<a href="mailto:wangfei.jimei@gmail.com" target="_blank">wangfei.jimei@gmail.com</a>> wrote:<o:p></o:p></p>
<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-right:0in">
<div>
<p class="MsoNormal">YuSeok, how did you attach the descriptor.bin to your coreboot? Did you follow the previous mail to include descriptor.bin with <span style="color:black">INCLUDE_ME and ME_PATH in .config?</span><o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<div>
<div>
<p class="MsoNormal">On Mon, Jun 20, 2016 at 6:46 AM, <span style="font-family:"Calibri",sans-serif">
김유석</span> <<a href="mailto:poplinux0@gmail.com" target="_blank">poplinux0@gmail.com</a>> wrote:<o:p></o:p></p>
</div>
</div>
<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-right:0in">
<div>
<div>
<div>
<p class="MsoNormal"><span style="font-family:GulimChe">Dear Sir.</span> <o:p></o:p></p>
<p><span style="font-family:GulimChe"><br>
My ENV</span><o:p></o:p></p>
<p><span style="font-family:GulimChe"> EVB : ADI SG-2440</span><o:p></o:p></p>
<p><span style="font-family:GulimChe"> source : official coreboot</span><o:p></o:p></p>
<p><span style="font-family:GulimChe"> FSP : intel FSP 4.0</span><o:p></o:p></p>
<p><span style="font-family:GulimChe"> </span><o:p></o:p></p>
<p><span style="font-family:GulimChe">I was successfully build-up the coreboot and successfully boot-up my EVB.</span><o:p></o:p></p>
<p><o:p> </o:p></p>
<p><span style="font-family:GulimChe">But My EVB's GbE is not activated(not running.)</span><o:p></o:p></p>
<p><o:p> </o:p></p>
<p><span style="font-family:GulimChe">So, I was try to boot using the original OEM bios(from ADI).
<b>This image is actvate the GbE</b>.</span><o:p></o:p></p>
<p><o:p> </o:p></p>
<p><span style="font-family:GulimChe">Another developer was same quetion to Coreboot communite. And He is resolved this issue.</span><o:p></o:p></p>
<p><span style="font-family:GulimChe"><a href="https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html" target="_blank">https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html</a></span><o:p></o:p></p>
<p><o:p> </o:p></p>
<p><span style="font-family:GulimChe">This guy's said that "Must add the descriptor.bin to coreboot.bin".</span><o:p></o:p></p>
<p><o:p> </o:p></p>
<p><span style="font-family:GulimChe">So, I was extract the descriptor.bin from ADI's coreboot.bin
</span><o:p></o:p></p>
<p><span style="font-family:GulimChe">And successfully attached the descriptor.bin to my coreboot.bin.</span><o:p></o:p></p>
<p><span style="font-family:GulimChe"> <b>oem_dumped.bin => ADI's default coreboot.bin, This image are activated the GbE.</b></span><o:p></o:p></p>
<p><span style="font-family:GulimChe"> <b>poplinux@raw bins $ ></b> ./ifdtool -x src/oem_dumped.bin
<br>
File src/oem_dumped.bin is 8388608 bytes <br>
Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff <br>
Flash Region 1 (BIOS): 00010000 - 007fffff <br>
Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused)<br>
Flash Region 3 (GbE): 00fff000 - 00000fff (unused)<br>
Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)</span><o:p></o:p></p>
<p><span style="font-family:GulimChe"> <b>poplinux@raw bins $ ></b> ln -s ./flashregion_0_flashdescriptor.bin descriptor.bin<br>
<b>poplinux@raw bins $ ></b> ./ifdtool -d ./descriptor.bin <br>
File ./descriptor.bin is 65536 bytes<br>
FLMAP0: 0x01040003<br>
NR: 1<br>
FRBA: 0x40<br>
NC: 1<br>
FCBA: 0x30<br>
FLMAP1: 0x09100206<br>
ISL: 0x09<br>
FPSBA: 0x100<br>
NM: 2<br>
FMBA: 0x60<br>
FLMAP2: 0x00210020<br>
PSL: 0x2100<br>
FMSBA: 0x200<br>
FLUMAP1: 0x000002e0<br>
Intel ME VSCC Table Length (VTL): 2<br>
Intel ME VSCC Table Base Address (VTBA): 0x000e00<br>
<br>
ME VSCC table:<br>
JID0: 0x001740ef<br>
SPI Componend Device ID 1: 0x17<br>
SPI Componend Device ID 0: 0x40<br>
SPI Componend Vendor ID: 0xef<br>
VSCC0: 0x20052005<br>
Lower Erase Opcode: 0x20<br>
Lower Write Enable on Write Status: 0x50<br>
Lower Write Status Required: No<br>
Lower Write Granularity: 64 bytes<br>
Lower Block / Sector Erase Size: 4KB<br>
Upper Erase Opcode: 0x20<br>
Upper Write Enable on Write Status: 0x50<br>
Upper Write Status Required: No<br>
Upper Write Granularity: 64 bytes<br>
Upper Block / Sector Erase Size: 4KB<br>
<br>
OEM Section:<br>
00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00<br>
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
<br>
Found Region Section<br>
FLREG0: 0x000f0000<br>
Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff <br>
FLREG1: 0x07ff0010<br>
Flash Region 1 (BIOS): 00010000 - 007fffff <br>
FLREG2: 0x00000fff<br>
Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused)<br>
FLREG3: 0x00000fff<br>
Flash Region 3 (GbE): 00fff000 - 00000fff (unused)<br>
FLREG4: 0x00000fff<br>
Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)<br>
<br>
Found Component Section<br>
FLCOMP 0x09200024<br>
Dual Output Fast Read Support: not supported<br>
Read ID/Read Status Clock Frequency: 33MHz<br>
Write/Erase Clock Frequency: 33MHz<br>
Fast Read Clock Frequency: 33MHz<br>
Fast Read Support: not supported<br>
Read Clock Frequency: 20MHz<br>
Component 2 Density: 8MB<br>
Component 1 Density: 8MB<br>
FLILL 0x00000000<br>
Invalid Instruction 3: 0x00<br>
Invalid Instruction 2: 0x00<br>
Invalid Instruction 1: 0x00<br>
Invalid Instruction 0: 0x00<br>
FLPB 0x00000000<br>
Flash Partition Boundary Address: 0x000000<br>
<br>
Found PCH Strap Section<br>
PCHSTRP0: 0x00080002<br>
PCHSTRP1: 0x00000000<br>
PCHSTRP2: 0x00000000<br>
PCHSTRP3: 0x00000003<br>
PCHSTRP4: 0x0000007f<br>
PCHSTRP5: 0x007fffc0<br>
PCHSTRP6: 0x0001c7c0<br>
PCHSTRP7: 0x00000624<br>
PCHSTRP8: 0x00000000<br>
PCHSTRP9: 0xffffffff<br>
PCHSTRP10: 0xffffffff<br>
PCHSTRP11: 0xffffffff<br>
PCHSTRP12: 0xffffffff<br>
PCHSTRP13: 0xffffffff<br>
PCHSTRP14: 0xffffffff<br>
PCHSTRP15: 0xffffffff<br>
PCHSTRP16: 0xffffffff<br>
PCHSTRP17: 0xffffffff<br>
<br>
Found Master Section<br>
FLMSTR1: 0x1f1f0000 (Host CPU/BIOS)<br>
Platform Data Region Write Access: enabled<br>
GbE Region Write Access: enabled<br>
Intel ME Region Write Access: enabled<br>
Host CPU/BIOS Region Write Access: enabled<br>
Flash Descriptor Write Access: enabled<br>
Platform Data Region Read Access: enabled<br>
GbE Region Read Access: enabled<br>
Intel ME Region Read Access: enabled<br>
Host CPU/BIOS Region Read Access: enabled<br>
Flash Descriptor Read Access: enabled<br>
Requester ID: 0x0000<br>
<br>
FLMSTR2: 0x08090118 (Intel ME)<br>
Platform Data Region Write Access: disabled<br>
GbE Region Write Access: enabled<br>
Intel ME Region Write Access: disabled<br>
Host CPU/BIOS Region Write Access: disabled<br>
Flash Descriptor Write Access: disabled<br>
Platform Data Region Read Access: disabled<br>
GbE Region Read Access: enabled<br>
Intel ME Region Read Access: disabled<br>
Host CPU/BIOS Region Read Access: disabled<br>
Flash Descriptor Read Access: enabled<br>
Requester ID: 0x0118<br>
<br>
FLMSTR3: 0xffffffff (GbE)<br>
Platform Data Region Write Access: enabled<br>
GbE Region Write Access: enabled<br>
Intel ME Region Write Access: enabled<br>
Host CPU/BIOS Region Write Access: enabled<br>
Flash Descriptor Write Access: enabled<br>
Platform Data Region Read Access: enabled<br>
GbE Region Read Access: enabled<br>
Intel ME Region Read Access: enabled<br>
Host CPU/BIOS Region Read Access: enabled<br>
Flash Descriptor Read Access: enabled<br>
Requester ID: 0xffff<br>
<br>
Found Processor Strap Section<br>
????: 0xffffffff<br>
????: 0xffffffff<br>
????: 0xffffffff<br>
????: 0xffffffff</span><o:p></o:p></p>
<p><o:p> </o:p></p>
<p><span style="font-family:GulimChe">But GbE is still de-activated. boot log is see below.</span><o:p></o:p></p>
<p><o:p> </o:p></p>
<p><span style="font-family:GulimChe"> PCI: pci_scan_bus for bus 00<br>
PCI: 00:00.0 [8086/0000] ops<br>
PCI: 00:00.0 [8086/1f0e] enabled<br>
Capability: type 0x10 @ 0x40<br>
Capability: type 0x01 @ 0x80<br>
Capability: type 0x0d @ 0x88<br>
Capability: type 0x05 @ 0x90<br>
Capability: type 0x10 @ 0x40<br>
PCI: 00:01.0 subordinate bus PCI Express<br>
PCI: 00:01.0 [8086/1f10] enabled<br>
PCI: Static device PCI: 00:02.0 not found, disabling it.<br>
Capability: type 0x10 @ 0x40<br>
Capability: type 0x01 @ 0x80<br>
Capability: type 0x0d @ 0x88<br>
Capability: type 0x05 @ 0x90<br>
Capability: type 0x10 @ 0x40<br>
PCI: 00:03.0 subordinate bus PCI Express<br>
PCI: 00:03.0 [8086/1f12] enabled<br>
PCI: Static device PCI: 00:04.0 not found, disabling it.<br>
PCI: 00:0b.0 [8086/1f18] enabled<br>
PCI: 00:0e.0 [8086/1f14] enabled<br>
PCI: 00:0f.0 [8086/1f16] enabled<br>
PCI: 00:13.0 [8086/1f15] enabled<br>
<b><span style="color:red"> PCI: Static device PCI: 00:14.0 not found, disabling it.<br>
PCI: Static device PCI: 00:14.1 not found, disabling it.<br>
PCI: Static device PCI: 00:14.2 not found, disabling it.<br>
PCI: Static device PCI: 00:14.3 not found, disabling it</span></b>.</span><o:p></o:p></p>
<p><o:p> </o:p></p>
<p><span style="font-family:GulimChe">I don't have a any idea for activate the GbE.</span><o:p></o:p></p>
<p><o:p> </o:p></p>
<p><span style="font-family:GulimChe">Please advise to me.</span><o:p></o:p></p>
<p><span style="font-family:GulimChe">Thank you. </span><o:p></o:p></p>
<p><o:p> </o:p></p>
<p><o:p> </o:p></p>
<p><o:p> </o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="color:#888888">--<br>
coreboot mailing list: <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br>
<a href="https://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">https://www.coreboot.org/mailman/listinfo/coreboot</a></span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p><o:p> </o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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