<html>
<head>
<meta content="text/html; charset=utf-8" http-equiv="Content-Type">
</head>
<body bgcolor="#FFFFFF" text="#000000">
<div class="moz-cite-prefix">Dear Sir. <br>
<br>
Thank's your prompt reply.<br>
<br>
Your answer is very nice to me.<br>
<br>
Best regards,<br>
<br>
Kay.kim<br>
<br>
2016-06-30 오후 1:35에 Berth-Olof Bergman 이(가) 쓴 글:<br>
</div>
<blockquote
cite="mid:320FA738-D0DE-47E0-92CC-F0183157F5CA@winzenttech.com"
type="cite">
<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
Answers to your question follows below.
<div class=""><br class="">
</div>
<div class="">Best regards,</div>
<div class=""><br class="">
</div>
<div class="">B-O</div>
<div class=""><br class="">
<div>
<blockquote type="cite" class="">
<div class="">30 juni 2016 kl. 03:08 skrev 김유석 <<a
moz-do-not-send="true" href="mailto:poplinux0@gmail.com"
class=""><a class="moz-txt-link-abbreviated" href="mailto:poplinux0@gmail.com">poplinux0@gmail.com</a></a>>:</div>
<br class="Apple-interchange-newline">
<div class="">
<meta content="text/html; charset=utf-8"
http-equiv="Content-Type" class="">
<div bgcolor="#FFFFFF" text="#000000" class="">
<div class="moz-cite-prefix">Dear Sir. <br class="">
<br class="">
Thank's your answer.<br class="">
<br class="">
I have a some more question for you.<br class="">
<b class=""><br class="">
</b><b class="">1. Must create the coreboot.bin under
4MB?</b><br class="">
You mean, "<u class="">You must create the
coreboot.bin under 4MB size?</u>"<br class="">
Is it correct?<br class="">
<br class="">
If i create the 8MByte size, It will be <u class="">unstable</u>?
or <u class="">stable</u>?<br class="">
</div>
</div>
</div>
</blockquote>
The chipset is limited to map only 4GB for BIOS firmware.<br
class="">
<blockquote type="cite" class="">
<div class="">
<div bgcolor="#FFFFFF" text="#000000" class="">
<div class="moz-cite-prefix"> <br class="">
<b class="">2. 4GB or 4MB?</b><br class="">
You said to me that "The BIOS image is limited to 4GB
by hardware"<br class="">
Is it correct or you miss-typing?<br class="">
</div>
</div>
</div>
</blockquote>
This is correct.<br class="">
<blockquote type="cite" class="">
<div class="">
<div bgcolor="#FFFFFF" text="#000000" class="">
<div class="moz-cite-prefix"> <br class="">
<b class="">3. Why support 16MByte image the Kconfig
of coreboot?</b><br class="">
I don't understand that why support 16MByte imge the
Kconfig of coreboot.<br class="">
Is it <u class="">just misstake</u>? or have a <u
class="">any reason</u>?<br class="">
</div>
</div>
</div>
</blockquote>
More than 4MB may be supported on other architectures. <br
class="">
<blockquote type="cite" class="">
<div class="">
<div bgcolor="#FFFFFF" text="#000000" class="">
<div class="moz-cite-prefix"> <br class="">
<br class="">
<div class="">Best regards,</div>
<div class=""><br class="">
</div>
Kay.kim.<br class="">
<br class="">
<br class="">
2016-06-29 오후 5:57에 Berth-Olof Bergman 이(가) 쓴 글:<br
class="">
</div>
<blockquote
cite="mid:152A2B9E-7CB0-422A-8FCC-6733405FB839@winzenttech.com"
type="cite" class="">
<meta http-equiv="Content-Type" content="text/html;
charset=utf-8" class="">
Hi,
<div class=""><br class="">
</div>
<div class="">The BIOS image is limited to 4GB by
hardware. So the BIOS need to fit within the top 4GB
of the flash. Otherwise it will not work. You can
concatenate your 8GB images to one 16 GB image and
it will work. Thus your BIOS part will be in top of
first 8GB and last 8GB of the 16 MB flash.</div>
<div class=""><br class="">
</div>
<div class="">As only 4GB can be mapped into memory
that the CPU can read, it's pointless to use 16GB
flash or more, unless you need more space for TXE
(Trusted Execution Engine) applications. Only the
TXE Sparc processor can read the wasted memory.</div>
<div class=""><br class="">
</div>
<div class="">You can read all the memory using SPI
controller read cycles, but that is not generally a
good idea. </div>
<div class=""><br class="">
</div>
<div class="">Best regards,</div>
<div class=""><br class="">
</div>
<div class="">B-O Bergman</div>
<div class="">Winzent Technologies</div>
<div class=""><br class="">
<div class="">
<blockquote type="cite" class="">
<div class="">29 juni 2016 kl. 09:14 skrev 김유석
<<a moz-do-not-send="true"
class="moz-txt-link-abbreviated"
href="mailto:poplinux0@gmail.com">poplinux0@gmail.com</a>>:</div>
<br class="Apple-interchange-newline">
<div class="">
<div class="moz-cite-prefix"
style="font-family: Helvetica; font-size:
17px; font-style: normal; font-variant-caps:
normal; font-weight: normal; letter-spacing:
normal; orphans: auto; text-align: start;
text-indent: 0px; text-transform: none;
white-space: normal; widows: auto;
word-spacing: 0px;
-webkit-text-stroke-width: 0px;
background-color: rgb(255, 255, 255);">Dear
Sir.<span class="Apple-converted-space"> </span><br
class="">
<br class="">
This issue was resolved.<br class="">
<br class="">
Cause is<span class="Apple-converted-space"> </span><b
class="">"size of coreboot.bin"</b><br
class="">
<br class="">
<br class="">
My work history is see below.<br class="">
<br class="">
<br class="">
<font class="" color="#3333ff">1. Replace
the flash memory on my EVB</font><br
class="">
My SG-2440 is have a 8MByte flash memory,
But I'll use the 16MByte flash.<br class="">
So, I was replace the flash memory 8MByte
to 16MByte.<span
class="Apple-converted-space"> </span><br
class="">
<span class="Apple-converted-space"> </span><br
class="">
original flash : WINBOND W25Q64 (8MByte)<br
class="">
new flash : WINBOND W25Q128(16MByte)<br
class="">
<br class="">
<font class="" color="#3333ff">2. Change
value of "ROM chip size" 8 MB to 16 MB</font><br
class="">
<br class="">
<span
id="cid:part1.E9FC0D8F.D8E7AF12@gmail.com"
class=""><hcglehbmiikmmgbd.png></span><br
class="">
<br class="">
<br class="">
<font class="" color="#3333ff">3. run make</font><br
class="">
I was successfully build the coreboot.<br
class="">
and got a "coreboot.bin". It is 16MByte
size.<br class="">
<br class="">
<font class="" color="#cc0000"><b class=""><span
class="Apple-converted-space"> </span>But
this image is boot fail on my EVB</b></font><span
class="Apple-converted-space"> </span>=><b
class=""><span
class="Apple-converted-space"> </span>I
don't understand</b><br class="">
<br class="">
<font class="" color="#3333ff">4. revert
"ROM chip size"<span
class="Apple-converted-space"> </span></font><br
class="">
I was revert value of "ROM chip size" to
8MByte.<br class="">
And write to start address 0x800000 on
16MByte flash memory.<br class="">
<br class="">
=><span class="Apple-converted-space"> </span><b
class="">booting is success</b>,<span
class="Apple-converted-space"> </span><font
class="" color="#cc0000"><b class="">But
GbE is not running.</b></font><br
class="">
<br class="">
<font class="" color="#3333ff">5. replace
the flash memory chip 16MByte to 8MByte.</font><br
class="">
I'm try to replace the flash memoy 16MByte
to 8MByte.<span
class="Apple-converted-space"> </span><br
class="">
And write to start address 0x00 on 8MByte
flash memory.<span
class="Apple-converted-space"> </span><br
class="">
<br class="">
=><span class="Apple-converted-space"> </span><b
class="">booting is success</b>,<span
class="Apple-converted-space"> </span><b
class=""><font class="" color="#cc0000">GbE
is running.</font></b><br class="">
<br class="">
<br class="">
<br class="">
<br class="">
<b class="">Anyway</b>, I was success
"enable the GbE".<br class="">
<br class="">
But I don't understand this sistuation.<br
class="">
<br class="">
<br class="">
Have a any idea?<br class="">
<br class="">
Thank you.<span
class="Apple-converted-space"> </span><br
class="">
<br class="">
<br class="">
<br class="">
<br class="">
<br class="">
2016-06-25 오후 11:46에 Guckian, David 이(가) 쓴
글:<br class="">
</div>
<blockquote
cite="mid:EBFDAB01CECF7F49957DBFF067E4F797436C3811@IRSMSX108.ger.corp.intel.com"
type="cite" style="font-family: Helvetica;
font-size: 17px; font-style: normal;
font-variant-caps: normal; font-weight:
normal; letter-spacing: normal; orphans:
auto; text-align: start; text-indent: 0px;
text-transform: none; white-space: normal;
widows: auto; word-spacing: 0px;
-webkit-text-stroke-width: 0px;
background-color: rgb(255, 255, 255);"
class="">
<div class="WordSection1" style="page:
WordSection1;">
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class="">Hi,<o:p class=""></o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class=""><o:p class=""> </o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class="">You are using the
Intel Rangeley FSP 4.0 release.<o:p
class=""></o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class="">I assume that you
downloaded this from<span
class="Apple-converted-space"> </span><a
moz-do-not-send="true"
class="moz-txt-link-freetext"
href="http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html"><a class="moz-txt-link-freetext" href="http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html">http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html</a></a><o:p
class=""></o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class="">With this download
you should have received the
supporting documentation, including
the FSP Integration Guide.<o:p
class=""></o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class="">Also included in
the download you should have received
the RangeleyFsp.bsf file.<o:p class=""></o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class="">This BSF file can
be used with the Intel BCT, also
available on<span
class="Apple-converted-space"> </span><a
moz-do-not-send="true"
class="moz-txt-link-freetext"
href="http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html"><a class="moz-txt-link-freetext" href="http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html">http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html</a></a><span
class="Apple-converted-space"> </span>,
to configure settings in the Intel FSP
binary.<o:p class=""></o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class="">Review the FSP
Integration Guide for more info
regarding the FSP binary configuration
settings.<o:p class=""></o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class=""><o:p class=""> </o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class="">Maybe you have
configured the Rangeley FSP binary to
disable the GbE devices.<o:p class=""></o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class="">Use the BCT to
enable the GbE devices, look for the
“Enable LAN” option.<o:p class=""></o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class=""><o:p class=""> </o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class="">Also, coreboot has
the ability to overwrite these
settings via the UPD_DATA_REGION
structure.<o:p class=""></o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class="">Please search your
coreboot for PcdEnableLan, if found
make sure this is set to “1”.<o:p
class=""></o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class=""><o:p class=""> </o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class="">Regards,<o:p
class=""></o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class="">David<o:p class=""></o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><a
moz-do-not-send="true"
name="_MailEndCompose" class=""><span
style="font-size: 11pt; font-family:
Calibri, sans-serif; color: rgb(31,
73, 125);" class=""><o:p class=""> </o:p></span></a></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><a
moz-do-not-send="true"
name="_____replyseparator" class=""></a><b
class=""><span style="font-size: 11pt;
font-family: Calibri, sans-serif;"
class="">From:</span></b><span
style="font-size: 11pt; font-family:
Calibri, sans-serif;" class=""><span
class="Apple-converted-space"> </span>coreboot
[<a moz-do-not-send="true"
class="moz-txt-link-freetext"
href="mailto:coreboot-bounces@coreboot.org">mailto:coreboot-bounces@coreboot.org</a>]<span
class="Apple-converted-space"> </span><b
class="">On Behalf Of<span
class="Apple-converted-space"> </span></b>WANG
FEI<br class="">
<b class="">Sent:</b><span
class="Apple-converted-space"> </span>Thursday,
June 23, 2016 10:16 PM<br class="">
<b class="">To:</b><span
class="Apple-converted-space"> </span></span><span
style="font-size: 11pt;" class="">김유석</span><span
style="font-size: 11pt; font-family:
Calibri, sans-serif;" class=""><span
class="Apple-converted-space"> </span><a
moz-do-not-send="true"
class="moz-txt-link-rfc2396E"
href="mailto:poplinux0@gmail.com"><a class="moz-txt-link-rfc2396E" href="mailto:poplinux0@gmail.com"><poplinux0@gmail.com></a></a><br
class="">
<b class="">Cc:</b><span
class="Apple-converted-space"> </span>coreboot<span
class="Apple-converted-space"> </span><a
moz-do-not-send="true"
class="moz-txt-link-rfc2396E"
href="mailto:coreboot@coreboot.org"><a class="moz-txt-link-rfc2396E" href="mailto:coreboot@coreboot.org"><coreboot@coreboot.org></a></a><br
class="">
<b class="">Subject:</b><span
class="Apple-converted-space"> </span>Re:
[coreboot] The GbE is not activated on
my Board.<o:p class=""></o:p></span></div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times New
Roman', serif;" class=""><o:p class=""> </o:p></div>
<div class="">
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times
New Roman', serif;" class="">Can you
send me the descriptor.bin and your
coreboot image? I can review it.<o:p
class=""></o:p></div>
<div class="">
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times
New Roman', serif;" class=""><o:p
class=""> </o:p></div>
</div>
<div class="">
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times
New Roman', serif;" class="">BTW,
your image is running on Mohon Peak
platform, right? I just have one
Mohon Peak platform to test.<o:p
class=""></o:p></div>
</div>
</div>
<div class="">
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times
New Roman', serif;" class=""><o:p
class=""> </o:p></div>
<div class="">
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times
New Roman', serif;" class="">On Wed,
Jun 22, 2016 at 7:37 AM,<span
class="Apple-converted-space"> </span><span
style="font-family: Calibri,
sans-serif;" class="">김유석</span><span
class="Apple-converted-space"> </span><<a
moz-do-not-send="true"
class="moz-txt-link-abbreviated"
href="mailto:poplinux0@gmail.com"><a class="moz-txt-link-abbreviated" href="mailto:poplinux0@gmail.com">poplinux0@gmail.com</a></a>>
wrote:<o:p class=""></o:p></div>
<blockquote style="border-style: none
none none solid; border-left-color:
rgb(204, 204, 204);
border-left-width: 1pt; padding: 0in
0in 0in 6pt; margin-left: 4.8pt;
margin-right: 0in;" class="">
<div class="">
<div class="">
<div style="margin: 0in 0in
0.0001pt; font-size: 12pt;
font-family: 'Times New
Roman', serif;" class="">Dear
Sir.<span
class="Apple-converted-space"> </span><br
class="">
<br class="">
I have already defined the
"CONFIG_IFD_BIN_PATH"<br
class="">
<br class="">
<b class=""><span
class="Apple-converted-space"> </span>131
CONFIG_HAVE_IFD_BIN=y</b><br
class="">
308 #<br class="">
309 # Southbridge<br
class="">
310 #<br class="">
311 # CONFIG_AMD_SB_CIMX is
not set<br class="">
312 #
CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800
is not set<br class="">
313 #
CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
is not set<br class="">
314
CONFIG_SOUTH_BRIDGE_OPTIONS=y<br
class="">
315 #
CONFIG_SOUTHBRIDGE_INTEL_COMMON
is not set<br class="">
316 #
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO
is not set<br class="">
<b class=""> 317
CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y<br
class="">
318
CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"</b><br
class="">
<br class="">
And successfully add to
coreboot.bin<br class="">
<br class="">
<br class="">
poplinux@raw coreboot $ >
./ifdtool -d coreboot.bin<span
class="Apple-converted-space"> </span><br class="">
File src/oem_dumped.bin is
8388608 bytes<o:p class=""></o:p></div>
<div class="">
<div class="">
<p class="MsoNormal"
style="margin: 0in 0in
12pt; font-size: 12pt;
font-family: 'Times New
Roman', serif;">FLMAP0:
0x01040003<br class="">
NR: 1<br class="">
FRBA: 0x40<br
class="">
NC: 1<br class="">
FCBA: 0x30<br
class="">
FLMAP1: 0x09100206<br
class="">
ISL: 0x09<br
class="">
FPSBA: 0x100<br
class="">
NM: 2<br class="">
FMBA: 0x60<br
class="">
FLMAP2: 0x00210020<br
class="">
PSL: 0x2100<br
class="">
FMSBA: 0x200<br
class="">
FLUMAP1: 0x000002e0<br
class="">
Intel ME VSCC Table
Length (VTL): 2<br
class="">
Intel ME VSCC Table Base
Address (VTBA): 0x000e00<br
class="">
<br class="">
ME VSCC table:<br class="">
JID0: 0x001740ef<br
class="">
SPI Componend Device
ID 1: 0x17<br
class="">
SPI Componend Device
ID 0: 0x40<br
class="">
SPI Componend Vendor
ID: 0xef<br
class="">
VSCC0: 0x20052005<br
class="">
Lower Erase
Opcode:
0x20<br class="">
Lower Write Enable on
Write Status: 0x50<br
class="">
Lower Write Status
Required: No<br
class="">
Lower Write
Granularity: 64
bytes<br class="">
Lower Block / Sector
Erase Size: 4KB<br
class="">
Upper Erase
Opcode:
0x20<br class="">
Upper Write Enable on
Write Status: 0x50<br
class="">
Upper Write Status
Required: No<br
class="">
Upper Write
Granularity: 64
bytes<br class="">
Upper Block / Sector
Erase Size: 4KB<br
class="">
<br class="">
OEM Section:<br class="">
00: 31 31 35 32 31 35 30
39 32 30 00 00 00 00 00 00<br
class="">
10: 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00<br
class="">
20: 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00<br
class="">
30: 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00<br
class="">
<br class="">
Found Region Section<br
class="">
FLREG0: 0x000f0000<br
class="">
Flash Region 0 (Flash
Descriptor): 00000000 -
0000ffff<span
class="Apple-converted-space"> </span><br
class="">
FLREG1: 0x07ff0010<br
class="">
Flash Region 1 (BIOS):
00010000 - 007fffff<span
class="Apple-converted-space"> </span><br
class="">
FLREG2: 0x00000fff<br
class="">
Flash Region 2 (Intel
ME): 00fff000 - 00000fff
(unused)<br class="">
FLREG3: 0x00000fff<br
class="">
Flash Region 3 (GbE):
00fff000 - 00000fff
(unused)<br class="">
FLREG4: 0x00000fff<br
class="">
Flash Region 4 (Platform
Data): 00fff000 - 00000fff
(unused)<br class="">
<br class="">
Found Component Section<br
class="">
FLCOMP 0x09200024<br
class="">
Dual Output Fast Read
Support: not
supported<br class="">
Read ID/Read Status
Clock Frequency: 33MHz<br
class="">
Write/Erase Clock
Frequency: 33MHz<br
class="">
Fast Read Clock
Frequency: 33MHz<br
class="">
Fast Read
Support:
not supported<br class="">
Read Clock
Frequency:
20MHz<br class="">
Component 2
Density:
8MB<br class="">
Component 1
Density:
8MB<br class="">
FLILL 0x00000000<br
class="">
Invalid Instruction 3:
0x00<br class="">
Invalid Instruction 2:
0x00<br class="">
Invalid Instruction 1:
0x00<br class="">
Invalid Instruction 0:
0x00<br class="">
FLPB 0x00000000<br
class="">
Flash Partition Boundary
Address: 0x000000<br
class="">
<br class="">
Found PCH Strap Section<br
class="">
PCHSTRP0: 0x00080002<br
class="">
PCHSTRP1: 0x00000000<br
class="">
PCHSTRP2: 0x00000000<br
class="">
PCHSTRP3: 0x00000003<br
class="">
PCHSTRP4: 0x0000007f<br
class="">
PCHSTRP5: 0x007fffc0<br
class="">
PCHSTRP6: 0x0001c7c0<br
class="">
PCHSTRP7: 0x00000624<br
class="">
PCHSTRP8: 0x00000000<br
class="">
PCHSTRP9: 0xffffffff<br
class="">
PCHSTRP10: 0xffffffff<br
class="">
PCHSTRP11: 0xffffffff<br
class="">
PCHSTRP12: 0xffffffff<br
class="">
PCHSTRP13: 0xffffffff<br
class="">
PCHSTRP14: 0xffffffff<br
class="">
PCHSTRP15: 0xffffffff<br
class="">
PCHSTRP16: 0xffffffff<br
class="">
PCHSTRP17: 0xffffffff<br
class="">
<br class="">
Found Master Section<br
class="">
FLMSTR1: 0x1f1f0000
(Host CPU/BIOS)<br
class="">
Platform Data Region
Write Access: enabled<br
class="">
GbE Region Write
Access: enabled<br
class="">
Intel ME Region Write
Access: enabled<br
class="">
Host CPU/BIOS Region
Write Access: enabled<br
class="">
Flash Descriptor Write
Access: enabled<br
class="">
Platform Data Region
Read Access: enabled<br
class="">
GbE Region Read
Access: enabled<br
class="">
Intel ME Region Read
Access: enabled<br
class="">
Host CPU/BIOS Region
Read Access: enabled<br
class="">
Flash Descriptor Read
Access: enabled<br
class="">
Requester
ID:
0x0000<br class="">
<br class="">
FLMSTR2: 0x08090118
(Intel ME)<br class="">
Platform Data Region
Write Access: disabled<br
class="">
GbE Region Write
Access: enabled<br
class="">
Intel ME Region Write
Access: disabled<br
class="">
Host CPU/BIOS Region
Write Access: disabled<br
class="">
Flash Descriptor Write
Access: disabled<br
class="">
Platform Data Region
Read Access: disabled<br
class="">
GbE Region Read
Access: enabled<br
class="">
Intel ME Region Read
Access: disabled<br
class="">
Host CPU/BIOS Region
Read Access: disabled<br
class="">
Flash Descriptor Read
Access: enabled<br
class="">
Requester
ID:
0x0118<br class="">
<br class="">
FLMSTR3: 0xffffffff
(GbE)<br class="">
Platform Data Region
Write Access: enabled<br
class="">
GbE Region Write
Access: enabled<br
class="">
Intel ME Region Write
Access: enabled<br
class="">
Host CPU/BIOS Region
Write Access: enabled<br
class="">
Flash Descriptor Write
Access: enabled<br
class="">
Platform Data Region
Read Access: enabled<br
class="">
GbE Region Read
Access: enabled<br
class="">
Intel ME Region Read
Access: enabled<br
class="">
Host CPU/BIOS Region
Read Access: enabled<br
class="">
Flash Descriptor Read
Access: enabled<br
class="">
Requester
ID:
0xffff<br class="">
<br class="">
Found Processor Strap
Section<br class="">
????: 0xffffffff<br
class="">
????: 0xffffffff<br
class="">
????: 0xffffffff<br
class="">
????: 0xffffffff<br
class="">
<br class="">
<br class="">
<o:p class=""></o:p></p>
</div>
</div>
<div style="margin: 0in 0in
0.0001pt; font-size: 12pt;
font-family: 'Times New
Roman', serif;" class="">But,
GbE still not running.<br
class="">
<br class="">
Please advise to me.<span
class="Apple-converted-space"> </span><br
class="">
<br class="">
Thank you.<br class="">
<br class="">
<br class="">
<br class="">
<br class="">
<br class="">
<br class="">
<br class="">
2016-06-22<span
class="Apple-converted-space"> </span><span
style="font-family: Calibri,
sans-serif;" class="">오전</span><span
class="Apple-converted-space"> </span>12:54<span style="font-family:
Calibri, sans-serif;"
class="">에</span><span
class="Apple-converted-space"> </span>WANG
FEI<span
class="Apple-converted-space"> </span><span
style="font-family: Calibri,
sans-serif;" class="">이</span>(<span
style="font-family: Calibri,
sans-serif;" class="">가</span>)<span
class="Apple-converted-space"> </span><span style="font-family: Calibri,
sans-serif;" class="">쓴</span><span
class="Apple-converted-space"> </span><span style="font-family: Calibri,
sans-serif;" class="">글</span>:<o:p
class=""></o:p></div>
</div>
<div class="">
<div class="">
<blockquote style="margin-top:
5pt; margin-bottom: 5pt;"
class="">
<div class="">
<div style="margin: 0in
0in 0.0001pt; font-size:
12pt; font-family:
'Times New Roman',
serif;" class="">INCLUDE_ME
& ME_PATH was used
before, but it has
changed to IFD_BIN_PATH
recently. Did you
define IFD_BIN_PATH with
path/descriptor.bin? It
should work!<o:p
class=""></o:p></div>
</div>
<div class="">
<div style="margin: 0in
0in 0.0001pt; font-size:
12pt; font-family:
'Times New Roman',
serif;" class=""><o:p
class=""> </o:p></div>
<div class="">
<div style="margin: 0in
0in 0.0001pt;
font-size: 12pt;
font-family: 'Times
New Roman', serif;"
class="">On Tue, Jun
21, 2016 at 2:16 AM,<span
class="Apple-converted-space"> </span><span style="font-family: Calibri,
sans-serif;"
class="">김유석</span><span
class="Apple-converted-space"> </span><<a moz-do-not-send="true"
class="moz-txt-link-abbreviated"
href="mailto:poplinux0@gmail.com">poplinux0@gmail.com</a>> wrote:<o:p
class=""></o:p></div>
<blockquote
style="border-style:
none none none solid;
border-left-color:
rgb(204, 204, 204);
border-left-width:
1pt; padding: 0in 0in
0in 6pt; margin-left:
4.8pt; margin-right:
0in;" class="">
<div class="">
<div class="">
<div
style="margin:
0in 0in
0.0001pt;
font-size: 12pt;
font-family:
'Times New
Roman', serif;"
class="">Dear
Sir.<br class="">
<br class="">
Thank's your
prompt reply.<br
class="">
<br class="">
My coreboot
source code
download from
coreboot GIT and
ADI's coreboot
GIT. both.<br
class="">
<br class="">
This time, I
work on official
coreboot GIT(not
ADI's GIT, but i
can do ADI's
GIT)<br class="">
<br class="">
<br class="">
<br class="">
<b class="">-
attach the
descriptor.bin<br
class="">
<br class="">
</b> I was
select the<span
class="Apple-converted-space"> </span><span style="color: red;" class="">"CONFIG_HAVE_IFD_BIN",
"CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY"</span>, and fill-up the<span
class="Apple-converted-space"> </span><span
style="color:
red;" class="">"CONFIG_IFD_BIN_PATH".</span><br
class="">
And
descriptor.bin
is extract from
ADI's EVB.<br
class="">
<br class="">
<b class=""><span
class="Apple-converted-space"> </span>131 CONFIG_HAVE_IFD_BIN=y</b><br
class="">
308 #<br
class="">
309 #
Southbridge<br
class="">
310 #<br
class="">
311 #
CONFIG_AMD_SB_CIMX
is not set<br
class="">
312 #
CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800
is not set<br
class="">
313 #
CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
is not set<br
class="">
314
CONFIG_SOUTH_BRIDGE_OPTIONS=y<br
class="">
315 #
CONFIG_SOUTHBRIDGE_INTEL_COMMON
is not set<br
class="">
316 #
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO
is not set<br
class="">
<b class="">
317
CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y<br
class="">
318
CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"</b><br
class="">
<br class="">
<span
id="cid:part8.AE2EAC0C.69317DF1@gmail.com"
class=""><Brevbilaga.jpeg></span><br
class="">
<br class="">
<br class="">
<br class="">
<br class="">
<b class="">-
Not exist
"INCLUDE_ME"
and "ME_PATH"</b><br
class="">
<br class="">
I'm can't
setup the
"INCLUDE_ME" and
"ME_PATH"
Because thie
keyword is not
exist coreboot's
source tree.<br
class="">
<br class="">
I was try to
find the
"INCLUDE_ME" and
"ME_PATH" from
coreboot source,
But not exist
this keyword.<br
class="">
<br class="">
<span
class="Apple-converted-space"> </span><b
class="">poplinux@raw
coreboot $
> ls</b><br
class="">
3rdparty
Documentation
Makefile
README
cscope.out
src
toolchain.inc<br
class="">
COPYING
MAINTAINERS
Makefile.inc
build
payloads
tags util<br
class="">
<br class="">
<span
class="Apple-converted-space"> </span><b
class="">poplinux@raw
coreboot $
> grep
"INCLUDE_ME" *
-Rn</b><br
class="">
<br class="">
<span
class="Apple-converted-space"> </span><b
class="">poplinux@raw
coreboot $
> grep
"ME_PATH" *
-Rn</b><br
class="">
cscope.out:9055111:CONFIG_RESUME_PATH_SAME_AS_BOOT<br
class="">
cscope.out:16228575:CONFIG_RESUME_PATH_SAME_AS_BOOT<br
class="">
cscope.out:16229157:CONFIG_RESUME_PATH_SAME_AS_BOOT<br
class="">
src/cscope.out:354905:CONFIG_RESUME_PATH_SAME_AS_BOOT<br
class="">
src/cscope.out:7528183:CONFIG_RESUME_PATH_SAME_AS_BOOT<br
class="">
src/cscope.out:7528765:CONFIG_RESUME_PATH_SAME_AS_BOOT<br
class="">
src/vendorcode/google/chromeos/vboot2/vboot_logic.c:125:
if
(!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT))<br
class="">
src/vendorcode/google/chromeos/vboot2/vboot_logic.c:311:
if
(IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)
&&<br
class="">
src/drivers/intel/fsp1_1/romstage.c:181:
!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)
&&<br
class="">
src/Kconfig:540:config
RESUME_PATH_SAME_AS_BOOT<br class="">
<br class="">
<br class="">
Please advise to
me.<br class="">
<br class="">
Thank you.<br
class="">
<br class="">
<br class="">
<br class="">
<br class="">
2016-06-21<span
class="Apple-converted-space"> </span><span style="font-family: Calibri,
sans-serif;"
class="">오전</span><span
class="Apple-converted-space"> </span>6:58<span style="font-family:
Calibri,
sans-serif;"
class="">에</span><span
class="Apple-converted-space"> </span>WANG FEI<span
class="Apple-converted-space"> </span><span
style="font-family: Calibri, sans-serif;" class="">이</span>(<span
style="font-family:
Calibri,
sans-serif;"
class="">가</span>)<span
class="Apple-converted-space"> </span><span style="font-family: Calibri,
sans-serif;"
class="">쓴</span><span
class="Apple-converted-space"> </span><span style="font-family: Calibri,
sans-serif;"
class="">글</span>:<o:p
class=""></o:p></div>
</div>
<div class="">
<div class="">
<blockquote
style="margin-top:
5pt;
margin-bottom:
5pt;" class="">
<div class="">
<div
style="margin:
0in 0in
0.0001pt;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class="">Here
is a sample,<span
class="Apple-converted-space"> </span><o:p class=""></o:p></div>
<div class="">
<div
style="margin:
0in 0in
0.0001pt;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></div>
</div>
<div class="">
<div
style="margin:
0in 0in
0.0001pt;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class="">Please
select INCLUDE_ME to y and set ME_PATH to point to your descriptor.bin
(Path/descriptor.bin,
refer to
FSP_FILE as a
sample).<o:p
class=""></o:p></div>
</div>
</div>
<div class="">
<div
style="margin:
0in 0in
0.0001pt;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></div>
<div class="">
<div
style="margin:
0in 0in
0.0001pt;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class="">On
Mon, Jun 20,
2016 at 10:48
PM, WANG FEI
<<a
moz-do-not-send="true"
class="moz-txt-link-abbreviated" href="mailto:wangfei.jimei@gmail.com"><a class="moz-txt-link-abbreviated" href="mailto:wangfei.jimei@gmail.com">wangfei.jimei@gmail.com</a></a>>
wrote:<o:p
class=""></o:p></div>
<blockquote
style="border-style:
none none none
solid;
border-left-color:
rgb(204, 204,
204);
border-left-width:
1pt; padding:
0in 0in 0in
6pt;
margin-left:
4.8pt;
margin-right:
0in;" class="">
<div class="">
<div
style="margin:
0in 0in
0.0001pt;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class="">YuSeok,
how did you
attach the
descriptor.bin
to your
coreboot? Did
you follow the
previous mail
to include
descriptor.bin
with <span
style=""
class="">INCLUDE_ME
and ME_PATH in
.config?</span><o:p
class=""></o:p></div>
</div>
<div class="">
<div
style="margin:
0in 0in
0.0001pt;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></div>
<div class="">
<div class="">
<div class="">
<div
style="margin:
0in 0in
0.0001pt;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class="">On
Mon, Jun 20,
2016 at 6:46
AM,<span
class="Apple-converted-space"> </span><span
style="font-family: Calibri, sans-serif;" class="">김유석</span><span
class="Apple-converted-space"> </span><<a
moz-do-not-send="true" class="moz-txt-link-abbreviated"
href="mailto:poplinux0@gmail.com"><a class="moz-txt-link-abbreviated" href="mailto:poplinux0@gmail.com">poplinux0@gmail.com</a></a>>
wrote:<o:p
class=""></o:p></div>
</div>
</div>
<blockquote
style="border-style:
none none none
solid;
border-left-color:
rgb(204, 204,
204);
border-left-width:
1pt; padding:
0in 0in 0in
6pt;
margin-left:
4.8pt;
margin-right:
0in;" class="">
<div class="">
<div class="">
<div class="">
<div
style="margin:
0in 0in
0.0001pt;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class="">Dear Sir.</span><o:p class=""></o:p></div>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class=""><br class="">
My ENV</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class=""> EVB : ADI SG-2440</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class=""> source : official coreboot</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class=""> FSP : intel FSP 4.0</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class=""> </span><o:p class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class="">I was successfully build-up the
coreboot and
successfully
boot-up my
EVB.</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class="">But My EVB's GbE is not
activated(not
running.)</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class="">So, I was try to boot using the
original OEM
bios(from
ADI).<span
class="Apple-converted-space"> </span><b
class="">This
image is
actvate the
GbE</b>.</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class="">Another developer was same
quetion to
Coreboot
communite. And
He is resolved
this issue.</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class=""><a moz-do-not-send="true"
class="moz-txt-link-freetext"
href="https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html"
style="color:
purple;
text-decoration:
underline;">https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html</a></span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class="">This guy's said that "Must add
the
descriptor.bin
to
coreboot.bin".</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class="">So, I was extract the
descriptor.bin
from ADI's
coreboot.bin</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class="">And successfully attached the
descriptor.bin
to my
coreboot.bin.</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class=""> <span
class="Apple-converted-space"> </span><b
class="">oem_dumped.bin
=> ADI's
default
coreboot.bin,
This image are
activated the
GbE.</b></span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class=""> <span
class="Apple-converted-space"> </span><b
class="">poplinux@raw
bins $ ></b><span
class="Apple-converted-space"> </span>./ifdtool -x src/oem_dumped.bin<span
class="Apple-converted-space"> </span><br class="">
File
src/oem_dumped.bin
is 8388608
bytes<span
class="Apple-converted-space"> </span><br
class="">
Flash
Region 0
(Flash
Descriptor):
00000000 -
0000ffff<span
class="Apple-converted-space"> </span><br class="">
Flash
Region 1
(BIOS):
00010000 -
007fffff<span
class="Apple-converted-space"> </span><br class="">
Flash
Region 2
(Intel ME):
00fff000 -
00000fff
(unused)<br
class="">
Flash
Region 3
(GbE):
00fff000 -
00000fff
(unused)<br
class="">
Flash
Region 4
(Platform
Data):
00fff000 -
00000fff
(unused)</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class=""> <span
class="Apple-converted-space"> </span><b
class="">poplinux@raw
bins $ ></b><span
class="Apple-converted-space"> </span>ln -s
./flashregion_0_flashdescriptor.bin
descriptor.bin<br
class="">
<span
class="Apple-converted-space"> </span><b
class="">poplinux@raw
bins $ ></b><span
class="Apple-converted-space"> </span>./ifdtool -d ./descriptor.bin<span
class="Apple-converted-space"> </span><br class="">
File
./descriptor.bin
is 65536 bytes<br
class="">
FLMAP0:
0x01040003<br
class="">
NR: 1<br
class="">
FRBA:
0x40<br
class="">
NC: 1<br
class="">
FCBA:
0x30<br
class="">
FLMAP1:
0x09100206<br
class="">
ISL:
0x09<br
class="">
FPSBA:
0x100<br
class="">
NM: 2<br
class="">
FMBA:
0x60<br
class="">
FLMAP2:
0x00210020<br
class="">
PSL:
0x2100<br
class="">
FMSBA:
0x200<br
class="">
FLUMAP1:
0x000002e0<br
class="">
Intel ME
VSCC Table
Length
(VTL):
2<br class="">
Intel ME
VSCC Table
Base Address
(VTBA):
0x000e00<br
class="">
<br class="">
ME VSCC
table:<br
class="">
JID0:
0x001740ef<br
class="">
SPI
Componend
Device ID
1:
0x17<br
class="">
SPI
Componend
Device ID
0:
0x40<br
class="">
SPI
Componend
Vendor
ID:
0xef<br
class="">
VSCC0:
0x20052005<br
class="">
Lower
Erase
Opcode:
0x20<br
class="">
Lower
Write Enable
on Write
Status: 0x50<br
class="">
Lower
Write Status
Required:
No<br class="">
Lower
Write
Granularity:
64 bytes<br
class="">
Lower
Block / Sector
Erase Size:
4KB<br
class="">
Upper
Erase
Opcode:
0x20<br
class="">
Upper
Write Enable
on Write
Status: 0x50<br
class="">
Upper
Write Status
Required:
No<br class="">
Upper
Write
Granularity:
64 bytes<br
class="">
Upper
Block / Sector
Erase Size:
4KB<br
class="">
<br class="">
OEM Section:<br
class="">
00: 31 31 35
32 31 35 30 39
32 30 00 00 00
00 00 00<br
class="">
10: 00 00 00
00 00 00 00 00
00 00 00 00 00
00 00 00<br
class="">
20: 00 00 00
00 00 00 00 00
00 00 00 00 00
00 00 00<br
class="">
30: 00 00 00
00 00 00 00 00
00 00 00 00 00
00 00 00<br
class="">
<br class="">
Found Region
Section<br
class="">
FLREG0:
0x000f0000<br
class="">
Flash
Region 0
(Flash
Descriptor):
00000000 -
0000ffff<span
class="Apple-converted-space"> </span><br class="">
FLREG1:
0x07ff0010<br
class="">
Flash
Region 1
(BIOS):
00010000 -
007fffff<span
class="Apple-converted-space"> </span><br class="">
FLREG2:
0x00000fff<br
class="">
Flash
Region 2
(Intel ME):
00fff000 -
00000fff
(unused)<br
class="">
FLREG3:
0x00000fff<br
class="">
Flash
Region 3
(GbE):
00fff000 -
00000fff
(unused)<br
class="">
FLREG4:
0x00000fff<br
class="">
Flash
Region 4
(Platform
Data):
00fff000 -
00000fff
(unused)<br
class="">
<br class="">
Found
Component
Section<br
class="">
FLCOMP
0x09200024<br
class="">
Dual
Output Fast
Read
Support:
not supported<br
class="">
Read
ID/Read Status
Clock
Frequency:
33MHz<br
class="">
Write/Erase
Clock
Frequency:
33MHz<br
class="">
Fast Read
Clock
Frequency:
33MHz<br
class="">
Fast Read
Support: not supported<br class="">
Read Clock
Frequency: 20MHz<br class="">
Component
2
Density:
8MB<br
class="">
Component
1
Density:
8MB<br
class="">
FLILL
0x00000000<br
class="">
Invalid
Instruction 3:
0x00<br
class="">
Invalid
Instruction 2:
0x00<br
class="">
Invalid
Instruction 1:
0x00<br
class="">
Invalid
Instruction 0:
0x00<br
class="">
FLPB
0x00000000<br
class="">
Flash
Partition
Boundary
Address:
0x000000<br
class="">
<br class="">
Found PCH
Strap Section<br
class="">
PCHSTRP0:
0x00080002<br
class="">
PCHSTRP1:
0x00000000<br
class="">
PCHSTRP2:
0x00000000<br
class="">
PCHSTRP3:
0x00000003<br
class="">
PCHSTRP4:
0x0000007f<br
class="">
PCHSTRP5:
0x007fffc0<br
class="">
PCHSTRP6:
0x0001c7c0<br
class="">
PCHSTRP7:
0x00000624<br
class="">
PCHSTRP8:
0x00000000<br
class="">
PCHSTRP9:
0xffffffff<br
class="">
PCHSTRP10:
0xffffffff<br
class="">
PCHSTRP11:
0xffffffff<br
class="">
PCHSTRP12:
0xffffffff<br
class="">
PCHSTRP13:
0xffffffff<br
class="">
PCHSTRP14:
0xffffffff<br
class="">
PCHSTRP15:
0xffffffff<br
class="">
PCHSTRP16:
0xffffffff<br
class="">
PCHSTRP17:
0xffffffff<br
class="">
<br class="">
Found Master
Section<br
class="">
FLMSTR1:
0x1f1f0000
(Host
CPU/BIOS)<br
class="">
Platform
Data Region
Write Access:
enabled<br
class="">
GbE Region
Write
Access:
enabled<br
class="">
Intel ME
Region Write
Access:
enabled<br
class="">
Host
CPU/BIOS
Region Write
Access:
enabled<br
class="">
Flash
Descriptor
Write
Access:
enabled<br
class="">
Platform
Data Region
Read Access:
enabled<br
class="">
GbE Region
Read
Access:
enabled<br
class="">
Intel ME
Region Read
Access:
enabled<br
class="">
Host
CPU/BIOS
Region Read
Access:
enabled<br
class="">
Flash
Descriptor
Read
Access:
enabled<br
class="">
Requester
ID: 0x0000<br class="">
<br class="">
FLMSTR2:
0x08090118
(Intel ME)<br
class="">
Platform
Data Region
Write Access:
disabled<br
class="">
GbE Region
Write
Access:
enabled<br
class="">
Intel ME
Region Write
Access:
disabled<br
class="">
Host
CPU/BIOS
Region Write
Access:
disabled<br
class="">
Flash
Descriptor
Write
Access:
disabled<br
class="">
Platform
Data Region
Read Access:
disabled<br
class="">
GbE Region
Read
Access:
enabled<br
class="">
Intel ME
Region Read
Access:
disabled<br
class="">
Host
CPU/BIOS
Region Read
Access:
disabled<br
class="">
Flash
Descriptor
Read
Access:
enabled<br
class="">
Requester
ID: 0x0118<br class="">
<br class="">
FLMSTR3:
0xffffffff
(GbE)<br
class="">
Platform
Data Region
Write Access:
enabled<br
class="">
GbE Region
Write
Access:
enabled<br
class="">
Intel ME
Region Write
Access:
enabled<br
class="">
Host
CPU/BIOS
Region Write
Access:
enabled<br
class="">
Flash
Descriptor
Write
Access:
enabled<br
class="">
Platform
Data Region
Read Access:
enabled<br
class="">
GbE Region
Read
Access:
enabled<br
class="">
Intel ME
Region Read
Access:
enabled<br
class="">
Host
CPU/BIOS
Region Read
Access:
enabled<br
class="">
Flash
Descriptor
Read
Access:
enabled<br
class="">
Requester
ID: 0xffff<br class="">
<br class="">
Found
Processor
Strap Section<br
class="">
????:
0xffffffff<br
class="">
????:
0xffffffff<br
class="">
????:
0xffffffff<br
class="">
????:
0xffffffff</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class="">But GbE is still de-activated.
boot log is
see below.</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class=""> PCI: pci_scan_bus for bus 00<br
class="">
PCI: 00:00.0
[8086/0000]
ops<br
class="">
PCI: 00:00.0
[8086/1f0e]
enabled<br
class="">
Capability:
type 0x10 @
0x40<br
class="">
Capability:
type 0x01 @
0x80<br
class="">
Capability:
type 0x0d @
0x88<br
class="">
Capability:
type 0x05 @
0x90<br
class="">
Capability:
type 0x10 @
0x40<br
class="">
PCI: 00:01.0
subordinate
bus PCI
Express<br
class="">
PCI: 00:01.0
[8086/1f10]
enabled<br
class="">
PCI: Static
device PCI:
00:02.0 not
found,
disabling it.<br
class="">
Capability:
type 0x10 @
0x40<br
class="">
Capability:
type 0x01 @
0x80<br
class="">
Capability:
type 0x0d @
0x88<br
class="">
Capability:
type 0x05 @
0x90<br
class="">
Capability:
type 0x10 @
0x40<br
class="">
PCI: 00:03.0
subordinate
bus PCI
Express<br
class="">
PCI: 00:03.0
[8086/1f12]
enabled<br
class="">
PCI: Static
device PCI:
00:04.0 not
found,
disabling it.<br
class="">
PCI: 00:0b.0
[8086/1f18]
enabled<br
class="">
PCI: 00:0e.0
[8086/1f14]
enabled<br
class="">
PCI: 00:0f.0
[8086/1f16]
enabled<br
class="">
PCI: 00:13.0
[8086/1f15]
enabled<br
class="">
<b class=""><span
style="color:
red;" class="">
PCI: Static
device PCI:
00:14.0 not
found,
disabling it.<br
class="">
PCI: Static
device PCI:
00:14.1 not
found,
disabling it.<br
class="">
PCI: Static
device PCI:
00:14.2 not
found,
disabling it.<br
class="">
PCI: Static
device PCI:
00:14.3 not
found,
disabling it</span></b>.</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class="">I don't have a any idea for
activate the
GbE.</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class="">Please advise to me.</span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="font-family: GulimChe;" class="">Thank you.<span
class="Apple-converted-space"> </span></span><o:p
class=""></o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></p>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></p>
</div>
<div
style="margin:
0in 0in
0.0001pt;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></div>
</div>
</div>
<div
style="margin:
0in 0in
0.0001pt;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><span
style="color:
rgb(136, 136,
136);"
class="">--<br
class="">
coreboot
mailing list:<span
class="Apple-converted-space"> </span><a moz-do-not-send="true"
class="moz-txt-link-abbreviated"
href="mailto:coreboot@coreboot.org" style="color: purple;
text-decoration:
underline;">coreboot@coreboot.org</a><br
class="">
<a
moz-do-not-send="true"
class="moz-txt-link-freetext"
href="https://www.coreboot.org/mailman/listinfo/coreboot"><a class="moz-txt-link-freetext" href="https://www.coreboot.org/mailman/listinfo/coreboot">https://www.coreboot.org/mailman/listinfo/coreboot</a></a></span><o:p
class=""></o:p></div>
</blockquote>
</div>
<div
style="margin:
0in 0in
0.0001pt;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></div>
</div>
</blockquote>
</div>
<div
style="margin:
0in 0in
0.0001pt;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></div>
</div>
</blockquote>
<p
style="margin-right:
0in;
margin-left:
0in;
font-size:
12pt;
font-family:
'Times New
Roman',
serif;"
class=""><o:p
class=""> </o:p></p>
</div>
</div>
</div>
</blockquote>
</div>
<div style="margin: 0in
0in 0.0001pt; font-size:
12pt; font-family:
'Times New Roman',
serif;" class=""><o:p
class=""> </o:p></div>
</div>
</blockquote>
<p style="margin-right: 0in;
margin-left: 0in; font-size:
12pt; font-family: 'Times
New Roman', serif;" class=""><o:p
class=""> </o:p></p>
</div>
</div>
</div>
</blockquote>
</div>
<div style="margin: 0in 0in 0.0001pt;
font-size: 12pt; font-family: 'Times
New Roman', serif;" class=""><o:p
class=""> </o:p></div>
</div>
</div>
<p style="margin-right: 0in; margin-left:
0in; font-size: 12pt; font-family: 'Times
New Roman', serif;" class="">--------------------------------------------------------------<br
class="">
Intel Research and Development Ireland
Limited<br class="">
Registered in Ireland<br class="">
Registered Office: Collinstown Industrial
Park, Leixlip, County Kildare<br class="">
Registered Number: 308263</p>
<p style="margin-right: 0in; margin-left:
0in; font-size: 12pt; font-family: 'Times
New Roman', serif;" class="">This e-mail
and any attachments may contain
confidential material for the sole use of
the intended recipient(s). Any review or
distribution by others is strictly
prohibited. If you are not the intended
recipient, please contact the sender and
delete all copies.</p>
</blockquote>
<p style="margin-right: 0in; margin-left: 0in;
font-size: 12pt; font-family: 'Times New
Roman', serif; font-style: normal;
font-variant-caps: normal; font-weight:
normal; letter-spacing: normal; orphans:
auto; text-align: start; text-indent: 0px;
text-transform: none; white-space: normal;
widows: auto; word-spacing: 0px;
-webkit-text-stroke-width: 0px;
background-color: rgb(255, 255, 255);"
class=""><br class="">
</p>
<span style="font-family: Helvetica;
font-size: 17px; font-style: normal;
font-variant-caps: normal; font-weight:
normal; letter-spacing: normal; orphans:
auto; text-align: start; text-indent: 0px;
text-transform: none; white-space: normal;
widows: auto; word-spacing: 0px;
-webkit-text-stroke-width: 0px;
background-color: rgb(255, 255, 255); float:
none; display: inline !important;" class="">--<span
class="Apple-converted-space"> </span></span><br
style="font-family: Helvetica; font-size:
17px; font-style: normal; font-variant-caps:
normal; font-weight: normal; letter-spacing:
normal; orphans: auto; text-align: start;
text-indent: 0px; text-transform: none;
white-space: normal; widows: auto;
word-spacing: 0px;
-webkit-text-stroke-width: 0px;
background-color: rgb(255, 255, 255);"
class="">
<span style="font-family: Helvetica;
font-size: 17px; font-style: normal;
font-variant-caps: normal; font-weight:
normal; letter-spacing: normal; orphans:
auto; text-align: start; text-indent: 0px;
text-transform: none; white-space: normal;
widows: auto; word-spacing: 0px;
-webkit-text-stroke-width: 0px;
background-color: rgb(255, 255, 255); float:
none; display: inline !important;" class="">coreboot
mailing list:<span
class="Apple-converted-space"> </span></span><a
moz-do-not-send="true"
class="moz-txt-link-abbreviated"
href="mailto:coreboot@coreboot.org"><a class="moz-txt-link-abbreviated" href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a></a><br
style="font-family: Helvetica; font-size:
17px; font-style: normal; font-variant-caps:
normal; font-weight: normal; letter-spacing:
normal; orphans: auto; text-align: start;
text-indent: 0px; text-transform: none;
white-space: normal; widows: auto;
word-spacing: 0px;
-webkit-text-stroke-width: 0px;
background-color: rgb(255, 255, 255);"
class="">
<a moz-do-not-send="true"
href="https://www.coreboot.org/mailman/listinfo/coreboot"
style="color: purple; text-decoration:
underline; font-family: Helvetica;
font-size: 17px; font-style: normal;
font-variant-caps: normal; font-weight:
normal; letter-spacing: normal; orphans:
auto; text-align: start; text-indent: 0px;
text-transform: none; white-space: normal;
widows: auto; word-spacing: 0px;
-webkit-text-stroke-width: 0px;
background-color: rgb(255, 255, 255);"
class="">https://www.coreboot.org/mailman/listinfo/coreboot</a></div>
</blockquote>
</div>
<br class="">
</div>
</blockquote>
<p class=""><br class="">
</p>
</div>
-- <br class="">
coreboot mailing list: <a moz-do-not-send="true"
href="mailto:coreboot@coreboot.org" class="">coreboot@coreboot.org</a><br
class="">
<a moz-do-not-send="true"
href="https://www.coreboot.org/mailman/listinfo/coreboot"
class="">https://www.coreboot.org/mailman/listinfo/coreboot</a></div>
</blockquote>
</div>
<br class="">
</div>
</blockquote>
<p><br>
</p>
</body>
</html>