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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">The CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER need to be set in order to find the microcode from cbfs.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Thanks,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">York<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><a name="_____replyseparator"></a><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> coreboot [mailto:coreboot-bounces@coreboot.org]
<b>On Behalf Of </b>Zoran Stojsavljevic<br>
<b>Sent:</b> Monday, July 04, 2016 2:33 PM<br>
<b>To:</b> Zeh, Werner <werner.zeh@siemens.com><br>
<b>Cc:</b> </span><span style="font-size:11.0pt;font-family:"Microsoft JhengHei",sans-serif">詹皓鈞</span><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> <ddtsssssss@gmail.com>; coreboot@coreboot.org<br>
<b>Subject:</b> Re: [coreboot] Bring up Intel Camelback Mountain Board with coreboot+FSP failed<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Hello Werner,<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Could be that you are correct. I know that INTEL PED team themselves up-streamed the whole BDW-DE Coreboot code into Coreboot. Here is the pointer proving that: <a href="https://www.coreboot.org/pipermail/coreboot-gerrit/2016-April/042490.html">https://www.coreboot.org/pipermail/coreboot-gerrit/2016-April/042490.html</a><o:p></o:p></p>
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<pre style="white-space:pre-wrap"><span style="color:black">+config CPU_MICROCODE_HEADER_FILES<o:p></o:p></span></pre>
<pre><span style="color:black">+ string<o:p></o:p></span></pre>
<pre><span style="color:black">+ default "../intel/cpu/broadwell_de/microcode/M1050663_07000001.h ../intel/cpu/broadwell_de/microcode/M1050662_0000000A.h ../intel/cpu/broadwell_de/microcode/MFF50661_F1000008.h"<o:p></o:p></span></pre>
<pre style="white-space:pre-wrap"><span style="color:black">The same I found in Jim's Coreboot config files:<o:p></o:p></span></pre>
<pre style="white-space:pre-wrap"><span style="color:black"># CONFIG_BUILD_WITH_FAKE_IFD is not set<o:p></o:p></span></pre>
<pre><span style="color:black">CONFIG_TTYS0_BASE=0x3f8<o:p></o:p></span></pre>
<pre><span style="color:black">CONFIG_CPU_MICROCODE_HEADER_FILES="../intel/cpu/broadwell_de/microcode/M1050663_07000001.h<o:p></o:p></span></pre>
<pre><span style="color:black">../intel/cpu/broadwell_de/microcode/M1050662_0000000A.h<o:p></o:p></span></pre>
<pre><span style="color:black">../intel/cpu/broadwell_de/microcode/MFF50661_F1000008.h"<o:p></o:p></span></pre>
<pre><span style="color:black">CONFIG_FSP_LOC=0xffeb0000<o:p></o:p></span></pre>
<pre><span style="color:black">CONFIG_SOC_INTEL_FSP_BROADWELL_DE=y<o:p></o:p></span></pre>
<pre><span style="color:black">York (Yang) is the one who can precisely answer on these questions. and maybe provide the latest MCUs, or at least these could be used for googl</span><span style="font-family:"Arial",sans-serif;color:black">the more recent BDX-DE MCUs.</span><span style="color:black"><o:p></o:p></span></pre>
<pre><span style="font-family:"Arial",sans-serif;color:black">Also, BDX-DE CPUID is important (I think for CPUIDs 0x50661, 0x50662, 0x50663 and assuming also 0x50664), so for different CPUIDs different MCU updates should be used (not 100% sure, thought).</span><span style="color:black"><o:p></o:p></span></pre>
<pre><span style="font-family:"Arial",sans-serif;color:black">Best Regards,</span><span style="color:black"><o:p></o:p></span></pre>
<pre><span style="font-family:"Arial",sans-serif;color:black">Zoran</span><span style="color:black"><o:p></o:p></span></pre>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Mon, Jul 4, 2016 at 12:39 PM, Zeh, Werner <<a href="mailto:werner.zeh@siemens.com" target="_blank">werner.zeh@siemens.com</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE" style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#1F497D">Hi Jim.</span><span lang="DE"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE" style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#1F497D"> </span><span lang="DE"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#1F497D">According to the Postcode it seems like you have no valid microcode for the used CPU.</span><span lang="DE"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#1F497D">In src/drivers/intel/fsp1_0/cache_as_ram.inc is the code which ends up in the endless loop while this
code is shown.</span><span lang="DE"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#1F497D"> </span><span lang="DE"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#1F497D">Check which CPU you really use on your mainboard and add the right microcode to you configuration.</span><span lang="DE"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#1F497D">This should solve your issue.</span><span lang="DE"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#1F497D"> </span><span lang="DE"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#1F497D">Werner</span><span lang="DE"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <span lang="DE"><o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><b><span lang="DE" style="font-size:10.0pt;font-family:"Tahoma",sans-serif">Von:</span></b><span lang="DE" style="font-size:10.0pt;font-family:"Tahoma",sans-serif"> coreboot [mailto:<a href="mailto:coreboot-bounces@coreboot.org" target="_blank">coreboot-bounces@coreboot.org</a>]
<b>Im Auftrag von </b>???<br>
<b>Gesendet:</b> Freitag, 1. Juli 2016 05:46<br>
<b>An:</b> <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br>
<b>Betreff:</b> [coreboot] Bring up Intel Camelback Mountain Board with coreboot+FSP failed</span><span lang="DE"><o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE">Dear Sir,<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE">I just clone the latest coreboot source code from
<a href="http://review.coreboot.org/p/coreboot" target="_blank">GIT</a> and FSP from
<a href="https://downloadcenter.intel.com/download/25701" target="_blank">Intel FSP website</a>.<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE">Using " make crossgcc-i386 CPU=4 " to setup the compilation environment.<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE">But the Camelback Mountain board could not bring up successfully, <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE">it always hang with POST CODE = <b>0xCE</b>.<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE">From the Intel FSP spec 1.0, it seems that system halt before loading FSP.<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE">Attached is my .config file, is there anyone hit the fail symptoms same as me and any idea to solve it?<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE"> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE">Thanks a lot,<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE">Jim<o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="DE"> <o:p></o:p></span></p>
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--<br>
coreboot mailing list: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
<a href="https://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">https://www.coreboot.org/mailman/listinfo/coreboot</a><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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