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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Hi Zoran,<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">thanks for checking back. I’m still on the issue (next to some other things), but haven’t made any progress yet. I also opened up a case at Intel
Premier Support and tried to follow their suggestions (Case 00053422).<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Anyway, I know the post_codes.h file. It defines POST_FSP_TEMP_RAM_INIT (0x90) which is the post code shown by coreboot just before it calls TempRamInit.
Then TempRamInit shows 0x52. Intel suggested that this is a microcode problem (i.e. the microcode doesn’t match the CPU stepping or platform), however, I’m pretty sure that this is not the case. At least I’ve taken a look at the CPUID signature (which is 0x406C4)
and the microcode header signature (which is 0x406C4). I also compared the platform ID bits from MSR 0x17 (which are 000, i.e. 1 << 000 = 1) with the platform ID field of the microcode (which is also 1). The microcode update facilities are documented in Intel’s
System Programming Guide (#325384).<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">I’m currently checking if coreboot is able to update the microcode while still in bootblock. There is a call to intel_update_microcode_from_cbfs()
in /src/soc/intel/braswell/bootblock/bootblock.c. Maybe, there is something sticking out…<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Regards,<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Alex<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">Von:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com]
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<b>Gesendet:</b> Montag, 25. Juli 2016 22:08<br>
<b>An:</b> Alexander Böcken<br>
<b>Cc:</b> coreboot@coreboot.org; york.yang@intel.com<br>
<b>Betreff:</b> Re: [coreboot] Microcode problem with Braswell CPU<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Hello Alex,<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">It is awhile... Opportunity just did struck (suddenly/plotzlich), so I am back!<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">While lurking around in Coreboot, trying to solve some "Mystery of digital Orga.ni.sms", I ran into very interesting file:<o:p></o:p></p>
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<p class="MsoNormal">./src/include/console/post_codes.h<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:9.5pt">Coreboot tree I am using: [zoran@localhost coreboot-09.06.2016]$ git describe<CR><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.5pt">4.4-455-g538b324<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.5pt"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.5pt">Maybe, it is worth looking into it. You tell us?<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.5pt"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.5pt">Zoran<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Tue, May 3, 2016 at 10:28 AM, Alexander Böcken <<a href="mailto:Alexander.Boecken@junger-audio.com" target="_blank">Alexander.Boecken@junger-audio.com</a>> wrote:<o:p></o:p></p>
<p class="MsoNormal">Hello Zoran,<br>
<br>
again, thanks for your clues to this problem. I don't think post code 0x52 is about memory configuration. The post code appears when I call TempRamInit which is supposed to enable Cache-as-RAM. Real memory is initialized at a later call to FspMemoryInit. coreboot
supplies the location of the microcode and a cachable region to TempRamInit. Additionally, there are some settings that can be applied to the FSP image with Intel's Binary Configuration Tool. I don't know if these are used during TempRamInit, but I'll try
and fiddle around with them.<br>
<br>
I agree, it would be helpful to have a list of post codes that can be output by FSP. Otherwise it's all speculation as what is wrong.<br>
<br>
Regards,<br>
Alex<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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