<div dir="ltr">Hello Cheng,<div><br></div><div>What I am getting from your emails and the net is the following:</div><div>CPUID 0x406C3 => 6 - Family, C - Model, Stepping - 3 (Si = C0)</div><div><br></div><div>Following the article I have posted before: <a href="http://www.anandtech.com/show/9806/intel-introduces-new-braswell-stepping-with-j3060-j3160-and-j3710" target="_blank" style="font-size:12.8px">http://www.anandtech.com/show/9806/intel-introduces-new-braswell-stepping-with-j3060-j3160-and-j3710</a> :</div><div>It is obvious that INTEL introduced new stepping Dx. In other words, CPUID 0x406C4 is stepping Dx (not sure which number x is for stepping 4).</div><div><br></div><div>Certainly you have to have different MCUs for the different stepping.</div><div><br></div><div>Now, I see the following from your last email:</div><div><span style="font-size:12.8px">2. In Coreboot I use microcode version M01406C440A N3060/N3160/x5-e800. version M01406C3363 for N3150.</span><br></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px">Here, you are correct, your N3150 is stepping C0, CPUID 0x406C3, MCU 0x363</span></div><div><span style="font-size:12.8px">N3060/N3160/x5-e800, they are all stepping Dx, CPUID 0x406C4, MCU 0x40A</span><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px">Only N3060 boots, and this is the lowest class (celeron) sku, maybe here there is a crucial difference why other skus do not boot.</span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px"><i><u>Other things to be of significant importance is how many channels and which DDR3 memory you are using on your boards?</u></i></span></div><div><span style="font-size:12.8px"><i><u>POST 0x52 (maybe?) suggests problems with MRC?!</u></i></span><br></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px">Best Regards,</span></div><div><span style="font-size:12.8px">Zoran</span></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jul 26, 2016 at 5:11 PM, cheng yichen <span dir="ltr"><<a href="mailto:blessyichen@gmail.com" target="_blank">blessyichen@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">HI Zoran<div><br></div><div>1Cherry Hill CRB CPU is N3150(cpuid is 406c3)</div><div><a href="http://2.in" target="_blank">2.in</a> coreboot I use microcode version M01406C440A N3060/N3160/x5-e800. version M01406C3363 for N3150.</div><div><br></div></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">2016-07-26 22:29 GMT+08:00 Zoran Stojsavljevic <span dir="ltr"><<a href="mailto:zoran.stojsavljevic@gmail.com" target="_blank">zoran.stojsavljevic@gmail.com</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><span><div><span style="font-size:12.8px"> > The issue can't be duplicated in cherryhill CRB. </span><br></div><div><span style="font-size:12.8px"><br></span></div></span><div><span style="font-size:12.8px">Hello Cheng,</span></div><div class="gmail_extra"><br></div><div class="gmail_extra">What BSW SoC type (N3xxx), which CPUID, and which stepping do you have in Cherry Hill CRB (IOTG one, seems N3060)? And also what MCU do you have there??</div><div class="gmail_extra"><br></div><div class="gmail_extra">Stepping is (at this point in time) very important (since you have to have correct MCU matching stepping)... I am not saying that this will anyhow solve the problem?!</div><div class="gmail_extra"><br></div><div class="gmail_extra">You can back-port IOTG BIOS, and read BIOS System Information page to find these info. And you (also, for sure) could open in Sales Force case #.... It will certainly put more</div><div class="gmail_extra">pressure on INTEL IOTG support, so they'll try to cope with the situation (although two different GEOs)... .. .</div><span><font color="#888888"><div class="gmail_extra"><br></div><div class="gmail_extra">Zoran</div></font></span><div><div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jul 26, 2016 at 10:48 AM, cheng yichen <span dir="ltr"><<a href="mailto:blessyichen@gmail.com" target="_blank">blessyichen@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hi all<div>I have the same issue and still can't solve it. I test those CPUs in my mainboard and only N3060 is workable with FSP. </div><div>I confuse why the same cpuid have different result. The issue can't be duplicated in cherryhill CRB. </div><div> </div><div><br></div><div></div><div><table border="0" cellpadding="0" cellspacing="0" style="width:1527px;color:rgb(51,51,51);font-family:arial,helvetica,sans-serif;font-size:12px;background-color:rgb(227,243,255)"><tbody><tr><td style="font-family:arial,helvetica,sans-serif;padding:4px 2px 4px 5px;border-width:0px 0px 1px;border-style:solid;border-color:rgb(237,237,237) rgb(237,237,237) rgb(227,222,184);vertical-align:middle"><div style="color:rgb(0,0,0);margin:0px;padding:0px"><br><br>N3060(cpuid:406C4) : boot successfully<br>N3160(cpuid:406C4) : hang up in check point 0x52<br>N3150(cpuid:406C3) : hang up in check point 0x52</div><div style="color:rgb(0,0,0);margin:0px;padding:0px">x5-e8000(cpuid:406c4): hang up in check point 0x52</div></td></tr></tbody></table></div></div><div class="gmail_extra"><br><div class="gmail_quote"><div><div>2016-07-26 15:27 GMT+08:00 Zoran Stojsavljevic <span dir="ltr"><<a href="mailto:zoran.stojsavljevic@gmail.com" target="_blank">zoran.stojsavljevic@gmail.com</a>></span>:<br></div></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div><div dir="ltr">Hello Alex,<div><br></div><div>I am not actively working for INTEL anymore (as my Linkedin profile suggests). For couple more months, my written agreement with them will come to the end, since we have some agreement in place for quite a while. I'll update my profile with the end date accordingly, when time comes. Here and everywhere else on the net, I speak only out of my IT experience/myself, so this has nothing to do with INTEL. In other words, opinions I write here are strictly mine, based on open net, open source, white paper documents and public data from INTEL, AMD and other companies.</div><div><br></div><div>There are other INTEL people watching this thread, so they might expedite your IPS/Sales Force case #. Good luck with that.</div><div><br></div><div>ATOM released wise, I was not too much involved with BSW (much more with BYT), so I have no idea if this what support suggested is correct, but it is (at least) worth trying.</div><div><br></div><div>Please, do note the following: <a href="http://www.anandtech.com/show/9806/intel-introduces-new-braswell-stepping-with-j3060-j3160-and-j3710" target="_blank">http://www.anandtech.com/show/9806/intel-introduces-new-braswell-stepping-with-j3060-j3160-and-j3710</a></div><div><br></div><div>Namely (excerpt from the article): <span style="font-family:arimo,sans-serif;font-size:14px;line-height:21px;background-color:rgb(246,246,246)"><i><font color="#444444">The Braswell update is a new stepping which adjusts the power consumption of the cores, raising the frequency, raising the TDP of the Pentium variants for a larger product separation, and renaming both the processor itself and the HD Graphics implementation. This change is referred to in the documentation </font><b><font color="#ff0000">as moving from the C-stepping to the D-stepping</font></b><font color="#444444">, which typically co-incides with a change in the way these processors are made (adjusted metal layer arrangement or lithography mask update).</font></i></span></div><div><br></div><div>Not sure how many D steppings are out there, you should ask/verify with support.</div><div><br></div><div>I myself now inspected <span style="font-size:12.8px">./src/include/console/post_</span><span style="font-size:12.8px">codes.h, and there is no 0x52 post code per say. This is why I asked several times PED FSP team to update/document non existent FSP post codes, so you all Coreboot-ers can have more clear picture what is going on with FSP boot, stages wise. :-)</span></div><div><br></div><div>Considering the latest you wrote, there are two files you also need to inspect:</div><div>src/cpu/intel/microcode/microcode.c<br></div><div>src/include/cpu/intel/microcode.h<br></div><div><br></div><div>Sincerely hope (some of) this helps,</div><div>Zoran</div></div><div><div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jul 26, 2016 at 8:04 AM, Alexander Böcken <span dir="ltr"><<a href="mailto:Alexander.Boecken@junger-audio.com" target="_blank">Alexander.Boecken@junger-audio.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Hi Zoran,<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">thanks for checking back. I’m still on the issue (next to some other things), but haven’t made any progress yet. I also opened up a case at Intel
Premier Support and tried to follow their suggestions (Case 00053422).<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Anyway, I know the post_codes.h file. It defines POST_FSP_TEMP_RAM_INIT (0x90) which is the post code shown by coreboot just before it calls TempRamInit.
Then TempRamInit shows 0x52. Intel suggested that this is a microcode problem (i.e. the microcode doesn’t match the CPU stepping or platform), however, I’m pretty sure that this is not the case. At least I’ve taken a look at the CPUID signature (which is 0x406C4)
and the microcode header signature (which is 0x406C4). I also compared the platform ID bits from MSR 0x17 (which are 000, i.e. 1 << 000 = 1) with the platform ID field of the microcode (which is also 1). The microcode update facilities are documented in Intel’s
System Programming Guide (#325384).<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">I’m currently checking if coreboot is able to update the microcode while still in bootblock. There is a call to intel_update_microcode_from_cbfs()
in /src/soc/intel/braswell/bootblock/bootblock.c. Maybe, there is something sticking out…<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Regards,<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Alex<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">Von:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Zoran Stojsavljevic [mailto:<a href="mailto:zoran.stojsavljevic@gmail.com" target="_blank">zoran.stojsavljevic@gmail.com</a>]
<br>
<b>Gesendet:</b> Montag, 25. Juli 2016 22:08<br>
<b>An:</b> Alexander Böcken<br>
<b>Cc:</b> <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a>; <a href="mailto:york.yang@intel.com" target="_blank">york.yang@intel.com</a><br>
<b>Betreff:</b> Re: [coreboot] Microcode problem with Braswell CPU<u></u><u></u></span></p><div><div>
<p class="MsoNormal"><u></u> <u></u></p>
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<p class="MsoNormal">Hello Alex,<u></u><u></u></p>
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<p class="MsoNormal"><u></u> <u></u></p>
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<p class="MsoNormal">It is awhile... Opportunity just did struck (suddenly/plotzlich), so I am back!<u></u><u></u></p>
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<p class="MsoNormal"><u></u> <u></u></p>
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<p class="MsoNormal">While lurking around in Coreboot, trying to solve some "Mystery of digital Orga.ni.sms", I ran into very interesting file:<u></u><u></u></p>
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<p class="MsoNormal">./src/include/console/post_codes.h<u></u><u></u></p>
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<p class="MsoNormal"><u></u> <u></u></p>
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<p class="MsoNormal"><span style="font-size:9.5pt">Coreboot tree I am using: [zoran@localhost coreboot-09.06.2016]$ git describe<CR><u></u><u></u></span></p>
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<p class="MsoNormal"><span style="font-size:9.5pt">4.4-455-g538b324<u></u><u></u></span></p>
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<p class="MsoNormal"><span style="font-size:9.5pt"><u></u> <u></u></span></p>
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<p class="MsoNormal"><span style="font-size:9.5pt">Maybe, it is worth looking into it. You tell us?<u></u><u></u></span></p>
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<p class="MsoNormal"><span style="font-size:9.5pt"><u></u> <u></u></span></p>
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<p class="MsoNormal"><span style="font-size:9.5pt">Zoran<u></u><u></u></span></p>
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<p class="MsoNormal"><u></u> <u></u></p>
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<p class="MsoNormal">On Tue, May 3, 2016 at 10:28 AM, Alexander Böcken <<a href="mailto:Alexander.Boecken@junger-audio.com" target="_blank">Alexander.Boecken@junger-audio.com</a>> wrote:<u></u><u></u></p>
<p class="MsoNormal">Hello Zoran,<br>
<br>
again, thanks for your clues to this problem. I don't think post code 0x52 is about memory configuration. The post code appears when I call TempRamInit which is supposed to enable Cache-as-RAM. Real memory is initialized at a later call to FspMemoryInit. coreboot
supplies the location of the microcode and a cachable region to TempRamInit. Additionally, there are some settings that can be applied to the FSP image with Intel's Binary Configuration Tool. I don't know if these are used during TempRamInit, but I'll try
and fiddle around with them.<br>
<br>
I agree, it would be helpful to have a list of post codes that can be output by FSP. Otherwise it's all speculation as what is wrong.<br>
<br>
Regards,<br>
Alex<u></u><u></u></p>
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<p class="MsoNormal"><u></u> <u></u></p>
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</div></div><br></div></div><span>--<br>
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