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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Hi Zoran,<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">yes, that’s the function. I also found the same information in the Intel docs.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">The docs say, the processor starts up with all caching disabled. So, the function marks the top 4 MB as write-protected memory and thus enables
caching for this region. The MTTR_DEF_TYPE MSR set the default memory configuration for all memory regions that were not explicitly configured by fixed/variable MTTRs. Intel recommends to use uncachable memory for all non-existing physical memory. As we haven’t
initialized DDR memory at this point, this seems fine to me.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">However, TempRamInit also seems to fuss about caching, regarding the FSP specification. So the code seems to interfere somehow, at least on my
CPU. I don’t know.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Best regards,<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Alex<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">Von:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com]
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<b>Gesendet:</b> Donnerstag, 28. Juli 2016 06:47<br>
<b>An:</b> Alexander Böcken<br>
<b>Cc:</b> cheng yichen; coreboot; york.yang@intel.com<br>
<b>Betreff:</b> Re: [coreboot] Microcode problem with Braswell CPU<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">> The function bootblock_cpu_init() (/src/soc/intel/braswell/bootblock/bootblock.c) contains a call to enable_rom_caching()</span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">This is the function, you are talking about:</span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">static void enable_rom_caching(void)</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">{</span><o:p></o:p></p>
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<p class="MsoNormal"><span class="gmail-apple-tab-span"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">
</span></span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">msr_t msr;</span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span class="gmail-apple-tab-span"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">
</span></span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">disable_cache();</span><o:p></o:p></p>
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<p class="MsoNormal"><span class="gmail-apple-tab-span"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">
</span></span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">/* Why only top 4MiB ? */</span><o:p></o:p></p>
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<p class="MsoNormal"><span class="gmail-apple-tab-span"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">
</span></span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);</span><o:p></o:p></p>
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<p class="MsoNormal"><span class="gmail-apple-tab-span"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">
</span></span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">enable_cache();</span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span class="gmail-apple-tab-span"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">
</span></span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">/* Enable Variable MTRRs */</span><o:p></o:p></p>
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<p class="MsoNormal"><span class="gmail-apple-tab-span"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">
</span></span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">msr.hi = 0x00000000;</span><o:p></o:p></p>
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<p class="MsoNormal"><span class="gmail-apple-tab-span"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">
</span></span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">msr.lo = 0x00000800;</span><o:p></o:p></p>
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<p class="MsoNormal"><span class="gmail-apple-tab-span"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">
</span></span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">wrmsr(MTRR_DEF_TYPE_MSR, msr);</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">}</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">I went to the <a href="https://www.google.de/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwj8pJm7m5XOAhWIQpoKHQ-pBQMQFggcMAA&url=http%3A%2F%2Fwww.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fprocessors%2Farchitectures-software-developer-manuals.html&usg=AFQjCNE0-V4xbVESpNFUdDMbSBXxnivKNw&sig2=6FShgOk_1L15UQbj6FlfYA&bvm=bv.128153897,d.bGg"><span style="font-size:13.5pt;font-family:"Arial","sans-serif";color:#660099">Intel®
64 and IA-32 Architectures Software Developer Manuals</span></a><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">to try to understand what really MTRR_DEF_TYPE_MSR refister (MSR 0x2FF) really means.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">After reading the appropriate parts to actually analyze this register, I got confused.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><img border="0" width="473" height="154" id="_x0000_i1025" src="cid:image002.png@01D1E8A3.BABBD400" alt="Inline image 1"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">First, I do not understand (as comment says correctly: Why only top 4MiB?), why not all 8MiB? Or maybe 16MiB, actual size of board flash?<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Second. I see that the type of this memory (msr.lo = 0x00000800;) is E - MTRR enable, FE disabled, type uncacheable - 0x00 (instead MTRR_TYPE_WRPROT - 0x05).<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Seems that this function was blindly copy/pasted from some other place... While creating BSW Coreboot context.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Best Regards,<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Zoran</span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p></o:p></span></p>
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