<div dir="ltr"><div>Hi Rafael,</div><div><br></div><div>This is a common problem for gdb (as your google search told you). Someone would need to add real mode <span style="line-height:1.5">(seg:offset etc)</span><span style="line-height:1.5"> to the gdb-stub. As you point out, other tools are better at doing the real mode disassembly.</span></div><div><span style="line-height:1.5"><br></span></div><div>Don't get too hung up on the real mode part, it switches modes pretty quick and you can get on with your day. This shouldn't hinder your understanding of the boot flow too much, now.</div><div><br></div><div>This person seems has a good description of the issue and a script that might help. <span style="line-height:1.5"><a href="http://ternet.fr/?p=gdb_real_mode">http://ternet.fr/?p=gdb_real_mode</a></span></div><div><span style="line-height:1.5"><br></span></div><div><span style="line-height:1.5">Marc</span></div><div><span style="line-height:1.5"><br></span></div></div><br><div class="gmail_quote"><div dir="ltr">On Tue, Aug 2, 2016 at 5:48 AM Rafael Machado <<a href="mailto:rafaelrodrigues.machado@gmail.com">rafaelrodrigues.machado@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hi everyone / Zoran<div><br></div><div>Thanks Zoran for the comments and don't worry about the name replacement :)<div><br></div><div>Just to clarify my question. </div><div>I already got to the same conclusion as you mentioned about the jmp instructions. (So your comments are well received because I see that I got how things are working)</div><div><br></div><div>What I would like to understand now, is why I don't see the same instructions at GDB and Radare2</div><div><br></div><img src="cid:1564b07202dd0cad2221" alt="pasted3" style="max-width:100%"><div>At this point. if I step gdb one more instruction I get to the following:</div><div><br></div><div><img src="cid:1564b138d9ed0cad2243" alt="pasted5" style="max-width:100%"><br></div><div><br></div><div>So at GDB I can see that the code that is being executed follow the flow that I can see at radare2.</div><div>The final question is:</div><div>Why can't I see the same disassembled code at GDB and radare2 ?</div><div>Do I need to execute some magic command at gdb besides these? </div></div></div><div dir="ltr"><div><div><br></div><div><div>set disassembly-flavor intel</div><div>set architecture i8086 </div><div>target remote localhost:1234</div></div><div><br></div><div><br></div></div></div><div dir="ltr"><div><div>Thanks everyone for the help</div><div>Rafael R. Machado</div><div><br></div><div><br></div><div class="gmail_quote"></div></div></div><div dir="ltr"><div><div class="gmail_quote"><div dir="ltr">Em ter, 2 de ago de 2016 às 01:31, Zoran Stojsavljevic <<a href="mailto:zoran.stojsavljevic@gmail.com" target="_blank">zoran.stojsavljevic@gmail.com</a>> escreveu:<br></div></div></div></div><div dir="ltr"><div><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Sorry, Rafael (do not know why I wrote Daniel)???</div><div dir="ltr"><div><br></div><div>Zoran</div></div></blockquote></div></div></div><div dir="ltr"><div><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="gmail_extra"><div class="gmail_quote">On Tue, Aug 2, 2016 at 6:30 AM, Zoran Stojsavljevic <span dir="ltr"><<a href="mailto:zoran.stojsavljevic@gmail.com" target="_blank">zoran.stojsavljevic@gmail.com</a>></span> wrote:<br></div></div></blockquote></div></div></div><div dir="ltr"><div><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hello Daniel,<div><br></div><div>I do not know if my answer will help you, but this what you see (I assume) in radare2 (which I am not aware of this package, I used in 1990/1991 to do lot of 8051 disassembling, namely INTEL 8052AH/80C52 8KB embedded BASIC - even wrote two part article in Elector Electronics about bugs and fixes in BASIC floating point):</div><div><br></div></div></blockquote></div></div></blockquote></div></div></div><div dir="ltr"><div><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div><img src="cid:ii_1564972be19c231c" alt="image.png" style="max-width:100%"><br></div></div></blockquote></div></div></blockquote></div></div></div><div dir="ltr"><div><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div><br></div><div>What I see here is the following: your CPU is in real 16-bit mode, using 20-bit memory (old x8086 1MB legacy), namely you are peaking into some jmp table, sort of (seems, function calls one after another, but no memory available, thus no stack)... You have here 3 byte short relative jumps one after another, with 16-bit Code Segment and 16-bit Instruction Pointer (example: CS -> 0xF000, IP -> 0x0040, which gives you the real 20-bit 0xF0000 + 0x00040 = 0xF0040 address), with short jump opcode (0xE9) and offset (in little endian format) to be added to current IP (pointing already to the next instruction).</div><div><br></div><div>This is at the very beginning of your BIOS (presumably), since as my best knowledge is, you need to jump from the initial location 0xF000:FFF0 somewhere back and switch from 16-bit Real to 32-bit Protected mode for CPU to continue to execute (this code seems still to set/prepare some required FW context in 16-bit mode).</div><div><br></div><div>Hope this helps,</div><div>Zoran</div></div></blockquote></div></div></blockquote></div></div></div><div dir="ltr"><div><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Aug 1, 2016 at 7:40 PM, Rafael Machado <span dir="ltr"><<a href="mailto:rafaelrodrigues.machado@gmail.com" target="_blank">rafaelrodrigues.machado@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hi everyone<div><br></div><div>I'm studying one firmware and to do that, as we talked on previous e-mail, I was using the Radare2.</div><div><br></div><div>At a given point I faced a "jmp di" instruction and I would like to know the value at a given register to understand </div><div>where the jmp is going to.</div><div><br></div><div>To do that I'm using Qemu, so I can check everything happening on the fly.</div><div>The problem I'm having now, is that the disas instruction at GDB is not working as I expected.</div><div><br></div><img src="cid:156472683a4d0cad2201" alt="pasted1" style="max-width:100%"><div>gdb output</div><div><br></div><div>The strange thing, is that when I compare the code flow, it really seems to do what I see at the Radare2 (except the fact that Qemu does not use the segment registers, but this is not a problem), but the gdb disas command doesn't present the code as I see at Radare2.</div><div><br></div><div><img src="cid:156472fde86d0cad2212" alt="pasted2" style="max-width:100%"><br></div><div>radare2 output</div><div><br></div><div>I did the following commands at gdb:</div><div><span style="line-height:normal;white-space:pre-wrap">set disassembly-flavor intel</span><br></div><div><pre style="word-wrap:break-word"><span style="line-height:normal;white-space:pre-wrap">set architecture i8086
target remote localhost:1234<br></span></pre></div><div><div><br></div><div>I searched on the internet ways to debug real-mode code, but didn't find any similar problem yet.</div><div>Does anyone have a guess of how could I solve this situation?</div><div><br></div><div><br></div><div>Thanks and Regards</div><div>Rafael R. Machado</div><div><br></div></div><div><div><br><div class="gmail_quote"><div dir="ltr">Em qua, 27 de jul de 2016 às 09:56, Rafael Machado <<a href="mailto:rafaelrodrigues.machado@gmail.com" target="_blank">rafaelrodrigues.machado@gmail.com</a>> escreveu:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hi Zoran, thanks a lot for expending your time to help!<div><br></div><div>I'll take a look. (It may take some time, but I will! )</div><div><br></div><div>Rafael R. Machado</div></div><br><div class="gmail_quote"><div dir="ltr">Em qua, 27 de jul de 2016 às 08:17, Zoran Stojsavljevic <<a href="mailto:zoran.stojsavljevic@gmail.com" target="_blank">zoran.stojsavljevic@gmail.com</a>> escreveu:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hello Rafael,<div><br></div><div>I am looking into disassembly pointed by you: </div></div><div dir="ltr"><div><br></div><div><div style="font-size:12.8px">> f000:0fcb 66b9ff020000 mov ecx, 0x2ff</div><div style="font-size:12.8px">> f000:0fd1 0f32 rdmsr ; read register 0x2ff (IA32_MTRR_DEF_TYPE)</div><div style="font-size:12.8px">> f000:0fd3 0fbae80b bts ax, 0xb ; Enable bit 11 (MTRR Enable).</div><div style="font-size:12.8px">> f000:0fd7 0fbae80a bts ax, 0xa ; Enable bit 10 (Fixed MTRR Enable).</div><div style="font-size:12.8px">> f000:0fdb 0f30 wrmsr ; Write changes to MTRR</div><div style="font-size:12.8px">> f000:0fdd 0f20c0 mov eax, cr0</div><div style="font-size:12.8px">> f000:0fe0 660fbaf01e btr eax, 0x1e ; Bit 30 means CD - Cache disabled.</div><div style="font-size:12.8px">> f000:0fe5 660fbaf01d btr eax, 0x1d ; Disable bit 29. NW - No Write-through</div><div style="font-size:12.8px">> f000:0fea 0f22c0 mov cr0, eax ; Write changes to CR0</div><div style="font-size:12.8px">> f000:0fed ffe7 jmp di</div><div style="font-size:12.8px">> f000:0fef 0f20c0 mov eax, cr0</div><div style="font-size:12.8px">> f000:0ff2 660fbae81e bts eax, 0x1e</div><div style="font-size:12.8px">> f000:0ff7 660fbae81d bts eax, 0x1d</div><div style="font-size:12.8px">> f000:0ffc 0f22c0 mov cr0, eax</div></div><div style="font-size:12.8px"><br></div></div><div dir="ltr"><div style="font-size:12.8px">Looks very similar like sequence in Coreboot ROMSTAGE (<span style="font-size:12.8px">src/cpu/intel/car/cache_as_ram.inc):</span></div><div style="font-size:12.8px"><span style="font-size:12.8px"><br></span></div><div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>/* We don't need CAR from now on. */</span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>/* Disable cache. */</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>movl<span style="white-space:pre-wrap"> </span>%cr0, %eax</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>orl<span style="white-space:pre-wrap"> </span>$CR0_CacheDisable, %eax</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>movl<span style="white-space:pre-wrap"> </span>%eax, %cr0</span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>/* Clear sth. */</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>movl<span style="white-space:pre-wrap"> </span>$MTRR_FIX_4K_C8000, %ecx</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>xorl<span style="white-space:pre-wrap"> </span>%edx, %edx</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>xorl<span style="white-space:pre-wrap"> </span>%eax, %eax</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>wrmsr</span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px">#if CONFIG_DCACHE_RAM_SIZE > 0x8000</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>movl<span style="white-space:pre-wrap"> </span>$MTRR_FIX_4K_C0000, %ecx</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>wrmsr</span></div><div><span style="font-size:12.8px">#endif</span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>/*</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span> * Set the default memory type and disable fixed</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span> * and enable variable MTRRs.</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span> */</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>movl<span style="white-space:pre-wrap"> </span>$MTRR_DEF_TYPE_MSR, %ecx</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>xorl<span style="white-space:pre-wrap"> </span>%edx, %edx</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>movl<span style="white-space:pre-wrap"> </span>$MTRR_DEF_TYPE_EN, %eax /* Enable variable and disable fixed MTRRs. */</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>wrmsr</span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>/* Enable cache. */</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>movl<span style="white-space:pre-wrap"> </span>%cr0, %eax</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>andl<span style="white-space:pre-wrap"> </span>$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax</span></div><div><span style="font-size:12.8px"><span style="white-space:pre-wrap"> </span>movl<span style="white-space:pre-wrap"> </span>%eax, %cr0</span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px">__main:</span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px">Please, check upon it. Please, pass to us your comments... If any?</span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px">Best Regards,</span></div><div><span style="font-size:12.8px">Zoran</span></div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jul 26, 2016 at 4:23 AM, Rafael Machado <span dir="ltr"><<a href="mailto:rafaelrodrigues.machado@gmail.com" target="_blank">rafaelrodrigues.machado@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Thanks a lot Zoran.<br>
I will!</div><span><font color="#888888"><span>
</span><p dir="ltr">Rafael</p></font></span><div><div><span>
</span><br><div class="gmail_quote"><div dir="ltr">Em seg, 25 de jul de 2016 14:13, Zoran Stojsavljevic <<a href="mailto:zoran.stojsavljevic@gmail.com" target="_blank">zoran.stojsavljevic@gmail.com</a>> escreveu:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hello Rafael,<div><br></div><div>Let me try hard... ;-)<br><div><br></div><div><div>Let us look into what actually we have here, in Coreboot: in bootblock phase, at the very beginning.</div><div>Let me tell you what I am looking into (what cb tree): [zoran@localhost coreboot-09.06.2016]$ git describe<CR></div><div><div>4.4-455-g538b324</div></div><div><br></div><div>Let us backtrace, to understand what is actual thread of execution:</div><div>src/arch/x86/prologue.inc</div><div>src/cpu/x86/16bit/entry16.inc</div><div>src/cpu/x86/16bit/reset16.inc</div><div>src/cpu/x86/32bit/entry32.inc</div><div>src/cpu/x86/sse_enable.inc</div><div>src/arch/x86/bootblock_simple.c</div><div><br></div><div>Please, carefully examine what I pointed/presented here... And let us know your thoughts.</div><div><br></div><div>Best Regards,</div><div>Zoran</div></div></div></div><div class="gmail_extra"><br><div class="gmail_quote"></div></div><div class="gmail_extra"><div class="gmail_quote">On Mon, Jul 25, 2016 at 6:03 PM, Rafael Machado <span dir="ltr"><<a href="mailto:rafaelrodrigues.machado@gmail.com" target="_blank">rafaelrodrigues.machado@gmail.com</a>></span> wrote:<br></div></div><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hi guys. Long time since my last e-mail.<div><br><div>It's hard to synchronize my day work with my firmware studies. Since my projects are more UEFI related I usually do not have to much time to study the legacy way, but It's really cool and Ill not give up :)</div><div><br></div><div>Since the last talk I was doing what everyone kindly proposed. (by the way thank you all for the guidance.)</div><div><br></div><div>Now I'm disassembly an old systems bios I have, but I cannot understand what is happening in a specific section of the code. (I'm using radare2 for my studies)</div><div><br></div><div>The code is:</div><div><br></div><div><div>f000:0fcb 66b9ff020000 mov ecx, 0x2ff</div><div>f000:0fd1 0f32 rdmsr ; read register 0x2ff (IA32_MTRR_DEF_TYPE)</div><div>f000:0fd3 0fbae80b bts ax, 0xb ; Enable bit 11 (MTRR Enable).</div><div>f000:0fd7 0fbae80a bts ax, 0xa ; Enable bit 10 (Fixed MTRR Enable).</div><div>f000:0fdb 0f30 wrmsr ; Write changes to MTRR</div><div>f000:0fdd 0f20c0 mov eax, cr0</div><div>f000:0fe0 660fbaf01e btr eax, 0x1e ; Bit 30 means CD - Cache disabled.</div><div>f000:0fe5 660fbaf01d btr eax, 0x1d ; Disable bit 29. NW - No Write-through</div><div>f000:0fea 0f22c0 mov cr0, eax ; Write changes to CR0</div><div>f000:0fed ffe7 jmp di</div><div>f000:0fef 0f20c0 mov eax, cr0</div><div>f000:0ff2 660fbae81e bts eax, 0x1e</div><div>f000:0ff7 660fbae81d bts eax, 0x1d</div><div>f000:0ffc 0f22c0 mov cr0, eax</div><div><br></div></div><div><br></div><div>Here is the code with my notes. I understand that some MTRR were set, and now the processor will be "configured".</div><div>We see at address <span style="line-height:1.5">f000:0fe0 and </span><span style="line-height:1.5">f000:0fe5 that the CR0 register is being changed and after that the changes are saved.</span></div><div><span style="line-height:1.5"><br></span></div><div><span style="line-height:1.5">Now I have two questions.</span></div><div><span style="line-height:1.5"><br></span></div><div><span style="line-height:1.5">1 - After CR0 changes get completed there is a "jmp di" instruction. This does not make any </span>sense<span style="line-height:1.5"> to me. Does anyone know why this is needed ? As far as I could check di value is 0x0 at this point. I think</span></div><div><span style="line-height:1.5"><br></span></div><div><span style="line-height:1.5">2 - After the "jmp di" a "CR0 Déjà vu" code is executed. Any idea why this is needed ?</span></div><div><span style="line-height:1.5"><br></span></div><div><span style="line-height:1.5">Thanks everyone</span></div><div><span style="line-height:1.5">Rafael R. Machado</span></div><div><br></div></div></div><br><div class="gmail_quote"><div dir="ltr">Em seg, 11 de jan de 2016 às 03:57, Alex G. <<a href="mailto:mr.nuke.me@gmail.com" target="_blank">mr.nuke.me@gmail.com</a>> escreveu:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">On 01/10/2016 10:23 AM, ron minnich wrote:<br>
> One thing I think you'd enjoy doing is building the qemu target, setting<br>
> up qemu with gdb, and just watching what happens, instruction by<br>
> instruction, as the system boots.<br>
<br>
One exercise I liked doing was to rewrite the entire boot flow, from<br>
reset vector to protected mode entry. Tested on qemu, put it on<br>
hardware, nothing burned.<br>
<br>
Alex<br>
<br>
> ron<br>
><br>
> On Sun, Jan 10, 2016 at 3:28 AM Rafael Machado<br>
> <<a href="mailto:rafaelrodrigues.machado@gmail.com" target="_blank">rafaelrodrigues.machado@gmail.com</a><br>
> <mailto:<a href="mailto:rafaelrodrigues.machado@gmail.com" target="_blank">rafaelrodrigues.machado@gmail.com</a>>> wrote:<br>
><br>
> Hi Peter and Rudolf.<br>
> Thanks for the answers and tips. They are realy helpfull !<br>
> I'll take a look.<br>
><br>
> Rafael R. Machado<br>
><br>
><br>
> Em Sáb, 9 de jan de 2016 17:19, Rudolf Marek <<a href="mailto:r.marek@assembler.cz" target="_blank">r.marek@assembler.cz</a><br>
> <mailto:<a href="mailto:r.marek@assembler.cz" target="_blank">r.marek@assembler.cz</a>>> escreveu:<br>
><br>
> Hi,<br>
><br>
> I guess your question is more general than the coreboot related<br>
> right?<br>
><br>
> If you have a firmware image dump of the flash (not the file you<br>
> download from<br>
> board vendor) then yes, first location to be executed is the<br>
> instruction located<br>
> 16 bytes before end of the image.<br>
><br>
> In coreboot see in build/ bootblock_inc.S which also has<br>
> reset16.inc and<br>
> entry16.inc which is a real start. Consult the Intel or AMD<br>
> manual to see the<br>
> CPU state after reset. The CPU starts in real mode, but CS base<br>
> is shifted to<br>
> last 64KB before end of 4GB address space. In general your CPU<br>
> starts in<br>
> compatible mode with 8086 manufactured in 1978.<br>
><br>
> Thanks<br>
> Rudolf<br>
><br>
> --<br>
> coreboot mailing list: <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br>
> <mailto:<a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a>><br>
> <a href="http://www.coreboot.org/mailman/listinfo/coreboot" rel="noreferrer" target="_blank">http://www.coreboot.org/mailman/listinfo/coreboot</a><br>
><br>
><br>
><span><font color="#888888"><br>
<br>
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