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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Hi Zoran,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"> For skylake refer src/soc/intel/skylake/bootblock/cache_as_ram.S around line 256. We are marking the ROMregion as WP and cacheable and programming
an MTRR appropriately.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">So, it’s not removed buts its being done while setting up Cache As Ram.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Regards,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Rizwan Qureshi<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><a name="_MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></a></p>
<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com]
<br>
<b>Sent:</b> Monday, August 8, 2016 12:33 PM<br>
<b>To:</b> coreboot <coreboot@coreboot.org>; Paul Menzel <paulepanter@users.sourceforge.net><br>
<b>Cc:</b> Qureshi, Rizwan <rizwan.qureshi@intel.com>; Ch, Naveenkrishna <naveenkrishna.ch@intel.com>; Yang, York <york.yang@intel.com><br>
<b>Subject:</b> Mistery of the function: static void enable_rom_caching(void)<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Hello community,<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">I was/got again today in Coreboot directory src/soc/intel/braswell/bootblock/bootblock.c looking at static void enable_rom_caching(void).<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Then, since Paul Menzel have announcement ([ANNOUNCEMENT] Support for Intel Kaby Lake), I went to look into src/soc/intel/skylake/bootblock/bootblock.c, but I did not find this function. Kaby Lake patches do not support this function as
well.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Then I did the following on my WIN 10 (using VMware workstation 12) VM Fedora 24:<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">[zoran@localhost intel]$ pwd<o:p></o:p></p>
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<p class="MsoNormal">/home/zoran/projects/coreboot/coreboot/src/soc/intel<o:p></o:p></p>
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<p class="MsoNormal">[zoran@localhost intel]$ git describe<o:p></o:p></p>
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<p class="MsoNormal">4.4-1038-gdd65ef8<o:p></o:p></p>
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<p class="MsoNormal">[zoran@localhost intel]$ ls -al<o:p></o:p></p>
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<p class="MsoNormal">total 48<o:p></o:p></p>
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<p class="MsoNormal">drwxrwxr-x. 12 4096 Aug 1 10:02 .<o:p></o:p></p>
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<p class="MsoNormal">drwxrwxr-x. 14 4096 Aug 1 10:02 ..<o:p></o:p></p>
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<p class="MsoNormal">drwxrwxr-x. 5 4096 Aug 1 10:02 apollolake<o:p></o:p></p>
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<p class="MsoNormal">drwxrwxr-x. 6 4096 Aug 1 10:02 baytrail<o:p></o:p></p>
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<p class="MsoNormal">drwxrwxr-x. 6 4096 Aug 1 10:02 braswell<o:p></o:p></p>
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<p class="MsoNormal">drwxrwxr-x. 6 4096 Aug 1 10:02 broadwell<o:p></o:p></p>
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<p class="MsoNormal">drwxrwxr-x. 3 4096 Aug 1 10:02 common<o:p></o:p></p>
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<p class="MsoNormal">drwxrwxr-x. 7 4096 Aug 1 10:02 fsp_baytrail<o:p></o:p></p>
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<p class="MsoNormal">drwxrwxr-x. 7 4096 Aug 1 10:02 fsp_broadwell_de<o:p></o:p></p>
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<p class="MsoNormal">drwxrwxr-x. 5 4096 Aug 1 10:02 quark<o:p></o:p></p>
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<p class="MsoNormal">drwxrwxr-x. 3 4096 Aug 1 10:02 sch<o:p></o:p></p>
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<p class="MsoNormal">drwxrwxr-x. 7 4096 Aug 1 10:02 skylake<o:p></o:p></p>
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<p class="MsoNormal">[zoran@localhost intel]$ grep -r enable_rom *<o:p></o:p></p>
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<p class="MsoNormal">baytrail/bootblock/bootblock.c:static void enable_rom_caching(void)<o:p></o:p></p>
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<p class="MsoNormal">baytrail/bootblock/bootblock.c: enable_rom_caching();<o:p></o:p></p>
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<p class="MsoNormal">braswell/bootblock/bootblock.c:static void enable_rom_caching(void)<o:p></o:p></p>
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<p class="MsoNormal">braswell/bootblock/bootblock.c: enable_rom_caching();<o:p></o:p></p>
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<p class="MsoNormal">broadwell/bootblock/cpu.c:static void enable_rom_caching(void)<o:p></o:p></p>
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<p class="MsoNormal">broadwell/bootblock/cpu.c: enable_rom_caching();<o:p></o:p></p>
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<p class="MsoNormal">fsp_baytrail/bootblock/bootblock.c:static void enable_rom_caching(void)<o:p></o:p></p>
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<p class="MsoNormal">fsp_baytrail/bootblock/bootblock.c: enable_rom_caching();<o:p></o:p></p>
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<p class="MsoNormal">[zoran@localhost intel]$<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">We see here that from skylake (also does not exists in apollolake) this function is dropped.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Any logical explanation for this mismatch?<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Thank you,<o:p></o:p></p>
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<p class="MsoNormal">Zoran<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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