<div dir="ltr"><div><div>The information missing from the mail is I requested to have that halt() added after console_init().<br><br></div>Also at least it was previously reported system was in a periodic reset-loop regardless of the halt() there, so sn active watchdog may be involved here. Looks like other boards <br></div><div>with same superio use call ite_kill_watchdog(), I don't know what it8718f_disable_reboot() does.<br><br></div><div>There was also suggestion to dump superio ID register on POST display to make sure LPC bus communication to superio works, but I did not hear back from that experiment.<br></div><div><br></div>Kyösti<br><div><div><div><div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Oct 26, 2016 at 4:36 AM, Riko Ho <span dir="ltr"><<a href="mailto:antonius.riko@gmail.com" target="_blank">antonius.riko@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Everyone,<br>
<br>
I tried to initialize UART on IT8718F and it stopped at 0xD2...<br>
Here's the complete function, any clues ?<br>
<br>
Cheers<br>
===============<br>
void mainboard_romstage_entry(<wbr>unsigned long bist)<br>
{<br>
int s3resume = 0, boot_mode = 0;<br>
<br>
if (bist == 0)<br>
enable_lapic();<br>
<br>
ich7_enable_lpc();<br>
post_code(0xD1);<br>
/* Enable SuperIO PM */<br>
//lpc47m15x_enable_serial(PME_<wbr>DEV, 0x680);<br>
//lpc47m15x_enable_serial(<wbr>SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */<br>
//enable_dev(SERIAL_DEV);<br>
//ite_conf_clkin();//needs a parameter, what is it ?<br>
<br>
/*<br>
04:24:31 AM) idwer: 24 or 48 MHz?<br>
<br>
(04:25:18 AM) idwer: how do you find out? run superiotool when<br>
having booted with the vendor bios, and look at register<br>
CR23<br>
*/<br>
//ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);<br>
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);<br>
<br>
<br>
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */<br>
//printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT BY RIKO HO...\n");<br>
//it8716f_enable_dev(SERIAL_<wbr>DEV, CONFIG_TTYS0_BASE);<br>
it8718f_disable_reboot(GPIO_<wbr>DEV);<br>
/* Set up the console */<br>
console_init();<br>
post_code(0xD2);<br>
printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT ...\n");<br>
halt();<br>
post_code(0xD3);<br>
<br>
<br>
<br>
/* Halt if there was a built in self test failure */<br>
report_bist_failure(bist);<br>
<br>
if (MCHBAR16(SSKPD) == 0xCAFE) {<br>
printk(BIOS_DEBUG, "soft reset detected.\n");<br>
boot_mode = 1;<br>
}<br>
<br>
/* Perform some early chipset initialization required<br>
* before RAM initialization can work<br>
*/<br>
i945_early_initialization();<br>
post_code(0xD4);<br>
s3resume = southbridge_detect_s3_resume()<wbr>;<br>
<br>
/* Enable SPD ROMs and DDR-II DRAM */<br>
enable_smbus();<br>
<br>
#if CONFIG_DEFAULT_CONSOLE_<wbr>LOGLEVEL > 8<br>
dump_spd_registers();<br>
#endif<br>
<br>
sdram_initialize(s3resume ? 2 : boot_mode, NULL);<br>
<br>
/* Perform some initialization that must run before stage2 */<br>
early_ich7_init();<br>
<br>
/* This should probably go away. Until now it is required<br>
* and mainboard specific<br>
*/<br>
rcba_config();<br>
<br>
/* Chipset Errata! */<br>
fixup_i945_errata();<br>
<br>
/* Initialize the internal PCIe links before we go into stage2 */<br>
i945_late_initialization(<wbr>s3resume);<br>
}<br>
<span class="HOEnZb"><font color="#888888"><br>
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</font></span></blockquote></div><br></div></div></div></div></div></div>