<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"><head><meta http-equiv=Content-Type content="text/html; charset=utf-8"><meta name=Generator content="Microsoft Word 14 (filtered medium)"><style><!--
/* Font Definitions */
@font-face
{font-family:Calibri;
panose-1:2 15 5 2 2 2 4 3 2 4;}
@font-face
{font-family:Tahoma;
panose-1:2 11 6 4 3 5 4 4 2 4;}
/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{margin:0cm;
margin-bottom:.0001pt;
font-size:12.0pt;
font-family:"Times New Roman","serif";}
a:link, span.MsoHyperlink
{mso-style-priority:99;
color:blue;
text-decoration:underline;}
a:visited, span.MsoHyperlinkFollowed
{mso-style-priority:99;
color:purple;
text-decoration:underline;}
p.MsoListParagraph, li.MsoListParagraph, div.MsoListParagraph
{mso-style-priority:34;
margin-top:0cm;
margin-right:0cm;
margin-bottom:0cm;
margin-left:36.0pt;
margin-bottom:.0001pt;
font-size:12.0pt;
font-family:"Times New Roman","serif";}
span.hoenzb
{mso-style-name:hoenzb;}
span.EmailStyle18
{mso-style-type:personal-reply;
font-family:"Calibri","sans-serif";
color:#1F497D;}
.MsoChpDefault
{mso-style-type:export-only;
font-family:"Calibri","sans-serif";
mso-fareast-language:EN-US;}
@page WordSection1
{size:612.0pt 792.0pt;
margin:2.0cm 42.5pt 2.0cm 3.0cm;}
div.WordSection1
{page:WordSection1;}
/* List Definitions */
@list l0
{mso-list-id:1029572572;
mso-list-type:hybrid;
mso-list-template-ids:484754394 68747281 68747289 68747291 68747279 68747289 68747291 68747279 68747289 68747291;}
@list l0:level1
{mso-level-text:"%1\)";
mso-level-tab-stop:none;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l0:level2
{mso-level-number-format:alpha-lower;
mso-level-tab-stop:none;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l0:level3
{mso-level-number-format:roman-lower;
mso-level-tab-stop:none;
mso-level-number-position:right;
text-indent:-9.0pt;}
@list l0:level4
{mso-level-tab-stop:none;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l0:level5
{mso-level-number-format:alpha-lower;
mso-level-tab-stop:none;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l0:level6
{mso-level-number-format:roman-lower;
mso-level-tab-stop:none;
mso-level-number-position:right;
text-indent:-9.0pt;}
@list l0:level7
{mso-level-tab-stop:none;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l0:level8
{mso-level-number-format:alpha-lower;
mso-level-tab-stop:none;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l0:level9
{mso-level-number-format:roman-lower;
mso-level-tab-stop:none;
mso-level-number-position:right;
text-indent:-9.0pt;}
ol
{margin-bottom:0cm;}
ul
{margin-bottom:0cm;}
--></style><!--[if gte mso 9]><xml>
<o:shapedefaults v:ext="edit" spidmax="1026" />
</xml><![endif]--><!--[if gte mso 9]><xml>
<o:shapelayout v:ext="edit">
<o:idmap v:ext="edit" data="1" />
</o:shapelayout></xml><![endif]--></head><body lang=RU link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Salut, Zoran!<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>The question isn’t specific to LynxPoint PCH. It is related to EHCI specification. Every southbridge with EHCI controller should support these registers in a right way.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Anyway, after months of investigation I solved this issue couple of days after I posted this letter.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>The solution was very simple, I just needed to explicitly disable XHCI through RCBA registers:<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> /* Disable unused devices (board specific) */<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS | PCH_DISABLE_XHCI),<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>It seems like “device pci 14.0 off end # USB3 XHCI” record in devicetree.cb is not enough. I spend so much time on this, cause USB worked perfectly without this RCBA register until S3 suspend/resume sequence.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>For complete answer, I’ll post solutions to my questions:<o:p></o:p></span></p><p class=MsoListParagraph style='text-indent:-18.0pt;mso-list:l0 level1 lfo1'><![if !supportLists]><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><span style='mso-list:Ignore'>1)<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>D3hot<o:p></o:p></span></p><p class=MsoListParagraph style='text-indent:-18.0pt;mso-list:l0 level1 lfo1'><![if !supportLists]><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><span style='mso-list:Ignore'>2)<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Yes<o:p></o:p></span></p><p class=MsoListParagraph style='text-indent:-18.0pt;mso-list:l0 level1 lfo1'><![if !supportLists]><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><span style='mso-list:Ignore'>3)<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Yes, and in resume BIOS sequence they still be suspended. But besides suspend bit all other bits in this F0-Fx register should be preserved (like current connection status)! If it isn’t so, something is wrong<o:p></o:p></span></p><p class=MsoListParagraph style='text-indent:-18.0pt;mso-list:l0 level1 lfo1'><![if !supportLists]><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><span style='mso-list:Ignore'>4)<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>It should be enabled automatically already in resume BIOS sequence<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] <br><b>Sent:</b> Tuesda</span><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>y, December 27, 2016 7:35 PM<br><b>To:</b> Аладышев Константин<br><b>Cc:</b> coreboot<br><b>Subject:</b> Re: [coreboot] USB EHCI power management<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>Privet Konstantin,<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Ja mogu i po Russkomu (russkij keyboard ne imeet dlja menja nikakogo smisla perekljucat6, tak cto ja po Russkomu naucilsja davnim, prezde cem (paru let prezde) ZX81 i Spektrum pojavilis6, no budu ja pisat6 po Anglijskij, tak cto ljudi Coreboot-a mogut ponjat6 ob cem mi zdes6 tolkujem/hozjataistvujem. :-)<o:p></o:p></p></div><div><p class=MsoNormal>_______<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>I do not think that people here, Coreboot people, have appropriate detailed documentation for Lynx Point (Series 8 PCH), which primarily serves to HSW (CORE 4) Family. It also served (as experimental PCH) to some SKL (Core 6) families. Before Sunrise Point (Series 10, I believe) PCH came to existence. About 14+ months ago.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>For the bigger picture, I'll suggest to you the following test scenario:<o:p></o:p></p></div><div><p class=MsoNormal>[1] You should do all of this what you have asked here with HSW (CORE 4) true BIOS, and then installing on the top of it any Linux distro (I use Fedora, I mastered it, but you can use any Linux distro of your free choice):<o:p></o:p></p></div><div><p class=MsoNormal> [A] After bringing BIOS up, and GRUB2, then Linux... You should exercise exactly the same scenario as you described with Coreboot BSP. Then, you should take any and every possible detailed log which you can (to compare with the same scenario using Coreboot).<o:p></o:p></p></div><div><p class=MsoNormal> [B] You should see if you have the same behavior as you describe it in your original email.<o:p></o:p></p></div><div><p class=MsoNormal>[2] You say/write heading: <b><i><u>USB EHCI power management</u></i></b>. What about: <b><i><u>USB xHCI power management</u></i></b> (there is duality there, in Lynx Point PCH, don't you know?)?<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>I hope this email helps somehow. :-)<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Zoran<o:p></o:p></p></div></div><div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>On Tue, Dec 27, 2016 at 10:24 AM, Аладышев Константин <<a href="mailto:aladyshev@nicevt.ru" target="_blank">aladyshev@nicevt.ru</a>> wrote:<o:p></o:p></p><p class=MsoNormal>I have a problem with USB EHCI on board with Lynxpoint-LP southbridge.<br><br>First of all system doesn't wakeup from USB devices from S3. EHCI controller<br>is listed in "/proc/acpi/wakeup" as "enabled" and GPE number is seemed to be<br>configured correctly to PME_B0, but it doesn't work.<br><br>More troubling issue that USB stops working after wakeup (for example from<br>power button).<br><br>In attempt to solve this issue I started to investigate how exactly EHCI<br>works in S3 suspend/resume sequence.<br><br>And I have some questions:<br><br>1) PCI_config: PWR_CNTL_STS register (54-55h)<br><br>What power state should enter EHCI controller when system enters S3? D0<br>state or D3hot ?<br><br>2) MEM_BASE: USB2.0_CMD (20-23h)<br><br>Is it correct, that system disables "Run/Stop (RS)" bit when system enters<br>S3?<br><br>3) MEM_BASE: RMHPORTSTSN (F0h)<br><br>Is it correct, that all ports became suspended when system enters S3?<br><br>4) Who is responsible to set "Run/Stop (RS)" and bring USB ports from<br>suspended state? BIOS or OS?<br><br>5) Is there any board in coreboot that has USB EHCI working correctly with<br>S3 suspend/resume?<br><span style='color:#888888'><br><br><br><span class=hoenzb>--</span><br><span class=hoenzb>coreboot mailing list: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a></span><br><span class=hoenzb><a href="https://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">https://www.coreboot.org/mailman/listinfo/coreboot</a></span></span><o:p></o:p></p></div><p class=MsoNormal><o:p> </o:p></p></div></div></body></html>