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<p><font size="2"><span style="font-size:10pt;">Q: do you use local xtal attached to Si52111-B5 to generate local PCIe 25MHz clock?</span></font></p>
<p><font size="2"><span style="font-size:10pt;">Zheng: yes<br>
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<font size="2"><span style="font-size:10pt;"></span></font></p>
<p><font size="2"><span style="font-size:10pt;">Q: If you dothis, my next question is how you synchronize these two clocks: Local<br>
PCIe 25 MHz and common reference clock from CPU?</span></font></p>
<p><font size="2"><span style="font-size:10pt;"><font size="2"><span style="font-size:10pt;">Zheng</span></font>: We do NOT sync these two.<br>
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Q: Since these two clocks, as I understand above scenario, are<br>
asynchronous to each other?!</span></font></p>
<p><font size="2"><span style="font-size:10pt;"><font size="2"><span style="font-size:10pt;"><font size="2"><span style="font-size:10pt;">Zheng</span></font>:
</span></font>yes. Asynchronous.</span></font></p>
<p><font size="2"><span style="font-size:10pt;"><br>
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<p><font size="2">The VPX connector does not have a PCIe ref clock signal, so we can not send CPU PCIe ref clock to
<br>
</font></p>
<p><font size="2">device. The PCIe spec says if the separate refclk on devices should be 100MHz <span>±</span> 300PPM, with SSC</font></p>
<p><font size="2">off. We believe our board meet this requirement. So we doubt the problem lies in PCI configration space.</font></p>
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<p><font size="2">Zheng<br>
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<div id="x_divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" color="#000000" face="Calibri, sans-serif"><b>From:</b> Zoran Stojsavljevic <zoran.stojsavljevic@gmail.com><br>
<b>Sent:</b> Thursday, January 12, 2017 9:22 AM<br>
<b>To:</b> Zheng Bao; Predrag Vidic<br>
<b>Cc:</b> coreboot@coreboot.org<br>
<b>Subject:</b> Re: [coreboot] Question about PCIe separate reference clock</font>
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<font size="2"><span style="font-size:10pt;">
<div class="PlainText">Hello Zheng,<br>
<br>
For decades, I've been FW/SW engineer, but I do understand a little<br>
bit of a HW. I have looked into the Si52111-B5 data sheet for<br>
clarification.<br>
<br>
My problem here is to understand, your use case: do you use local xtal<br>
attached to Si52111-B5 to generate local PCIe 25MHz clock? If you do<br>
this, my next question is how you synchronize these two clocks: Local<br>
PCIe 25 MHz and common reference clock from CPU?<br>
<br>
Since these two clocks, as I understand above scenario, are<br>
asynchronous to each other?!<br>
<br>
Please, clarify for us your use case.<br>
<br>
Thank you,<br>
Zoran<br>
_______<br>
<br>
On 1/12/17, Zheng Bao <fishbaoz@hotmail.com> wrote:<br>
> Our VPX design uses separate reference clock source, which is Si52111-B5 (No<br>
> spread), instead of common ref clock from CPU.<br>
> Now The system is unstable. Reading PCIE configuration space is unstable<br>
> too. (If we add some fly wire to make it work with common ref clock, the<br>
> system becomes stable.)<br>
><br>
> (abstracted from PCIe spec: 12 Slot Clock Configuration - This bit indicates<br>
> that the<br>
> component uses the same physical reference clock that the<br>
> platform provides on the connector. If the device uses an<br>
> independent clock irrespective of the presence of a reference<br>
> clock on the connector, this bit must be clear.<br>
> For a multi-Function device, each Function must report the<br>
> same value for this bit.)<br>
><br>
> Based on my understanding, the BIOS need to read bit "Slot Clock<br>
> Configurationclear" to see if<br>
> separate ref clock is used. BIOS then write bit "Common Clock<br>
> Configuration".<br>
><br>
> On our board, the bit "Slot Clock Configuration" is always 1, which I assume<br>
> should be 0.<br>
><br>
> My question is, how the hardware affect the bit "Slot Clock Configuration"?<br>
> How do we need to design our board to make the bit "Slot Clock<br>
> Configuration" be 0?<br>
><br>
> Thanks.<br>
><br>
> Zheng<br>
><br>
><br>
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