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<p class="MsoNormal"><span lang="EN-US">Our VPX design uses separate reference clock source, which is Si52111-B5 (No spread), instead of common ref clock from CPU.</span></p>
<p class="MsoNormal"><span lang="EN-US">Now The system is unstable. Reading PCIE configuration space is unstable too. (If we add some fly wire to make it work with common ref clock, the system becomes stable.)</span></p>
<p class="MsoNormal"><span lang="EN-US"> </span></p>
<p class="MsoNormal"><span lang="EN-US"></p>
<div>(abstracted from PCIe spec: 12 Slot Clock Configuration – This bit indicates that the<br>
component uses the same physical reference clock that the<br>
platform provides on the connector. If the device uses an<br>
independent clock irrespective of the presence of a reference<br>
clock on the connector, this bit must be clear.<br>
For a multi-Function device, each Function must report the<br>
same value for this bit.)</div>
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<p class="MsoNormal"><span lang="EN-US">Based on my understanding, the BIOS need to read bit "Slot Clock Configurationclear" to see if</span></p>
<p class="MsoNormal"><span lang="EN-US">separate ref clock is used. BIOS then write bit "Common Clock Configuration".</span></p>
<p class="MsoNormal"><span lang="EN-US"> </span></p>
<p class="MsoNormal"><span lang="EN-US">On our board, the bit "Slot Clock Configuration" is always 1, which I assume should be 0.</span></p>
<p class="MsoNormal"><span lang="EN-US"> </span></p>
<p class="MsoNormal"><span lang="EN-US">My question is, how the hardware affect the bit "Slot Clock Configuration"? How do we need to design our board to make the bit "Slot Clock Configuration" be 0?
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<p class="MsoNormal"><span lang="EN-US"> </span></p>
<p class="MsoNormal"><span lang="EN-US">Thanks.</span></p>
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<p class="MsoNormal"><span lang="EN-US">Zheng<br>
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