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<p>Here is the ref clk part. Please review.</p>
<p>No refclk routes to VPX connector.</p>
<p><br>
</p>
<p>Thanks.</p>
<p><br>
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<p>Zheng<br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" color="#000000" face="Calibri, sans-serif"><b>From:</b> Predrag Vidic <pvidic@gmail.com><br>
<b>Sent:</b> Thursday, January 12, 2017 6:53 PM<br>
<b>To:</b> Zheng Bao<br>
<b>Cc:</b> Zoran Stojsavljevic; coreboot@coreboot.org<br>
<b>Subject:</b> Re: [coreboot] Question about PCIe separate reference clock</font>
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<div dir="ltr">Hi Zheng,<br>
<br>
Without knowing the particular solution for the PCIe transmitter you have on your board, I'd check refclk pins on your design for the proper termination. The problem can be in irregular readings from the pins.<br>
<br>
Reragds,<br>
Predrag</div>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Thu, Jan 12, 2017 at 3:26 PM, Zheng Bao <span dir="ltr">
<<a href="mailto:fishbaoz@hotmail.com" target="_blank">fishbaoz@hotmail.com</a>></span> wrote:<br>
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<p><font size="2"><span style="font-size:10pt">Q: do you use local xtal attached to Si52111-B5 to generate local PCIe 25MHz clock?</span></font></p>
</span>
<p><font size="2"><span style="font-size:10pt">Zheng: yes<br>
</span></font></p>
<p><br>
<font size="2"><span style="font-size:10pt"></span></font></p>
<p><font size="2"><span style="font-size:10pt">Q: If you dothis, my next question is how you synchronize these two clocks: Local<span class=""><br>
PCIe 25 MHz and common reference clock from CPU?</span></span></font></p>
<p><font size="2"><span style="font-size:10pt"><font size="2"><span style="font-size:10pt">Zheng</span></font>: We do NOT sync these two.<br>
</span></font></p>
<p><font size="2"><span style="font-size:10pt"><br>
Q: Since these two clocks, as I understand above scenario, are<br>
asynchronous to each other?!</span></font></p>
<p><font size="2"><span style="font-size:10pt"><font size="2"><span style="font-size:10pt"><font size="2"><span style="font-size:10pt">Zheng</span></font>:
</span></font>yes. Asynchronous.</span></font></p>
<p><font size="2"><span style="font-size:10pt"><br>
</span></font></p>
<p><font size="2">The VPX connector does not have a PCIe ref clock signal, so we can not send CPU PCIe ref clock to
<br>
</font></p>
<p><font size="2">device. The PCIe spec says if the separate refclk on devices should be 100MHz <span>±</span> 300PPM, with SSC</font></p>
<p><font size="2">off. We believe our board meet this requirement. So we doubt the problem lies in PCI configration space.</font></p>
<p><font size="2"><br>
</font></p>
<p><font size="2">Zheng<br>
</font></p>
<p><font size="2"></font><br>
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<div id="m_1263023594929631817x_divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" color="#000000" face="Calibri, sans-serif"><b>From:</b> Zoran Stojsavljevic <<a href="mailto:zoran.stojsavljevic@gmail.com" target="_blank">zoran.stojsavljevic@gmail.com</a><wbr>><br>
<b>Sent:</b> Thursday, January 12, 2017 9:22 AM<br>
<b>To:</b> Zheng Bao; Predrag Vidic<br>
<b>Cc:</b> <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br>
<b>Subject:</b> Re: [coreboot] Question about PCIe separate reference clock</font>
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<div class="m_1263023594929631817PlainText">Hello Zheng,<br>
<br>
For decades, I've been FW/SW engineer, but I do understand a little<br>
bit of a HW. I have looked into the Si52111-B5 data sheet for<br>
clarification.<br>
<br>
My problem here is to understand, your use case: do you use local xtal<br>
attached to Si52111-B5 to generate local PCIe 25MHz clock? If you do<br>
this, my next question is how you synchronize these two clocks: Local<br>
PCIe 25 MHz and common reference clock from CPU?<br>
<br>
Since these two clocks, as I understand above scenario, are<br>
asynchronous to each other?!<br>
<br>
Please, clarify for us your use case.<br>
<br>
Thank you,<br>
Zoran<br>
_______<br>
<br>
On 1/12/17, Zheng Bao <<a href="mailto:fishbaoz@hotmail.com" target="_blank">fishbaoz@hotmail.com</a>> wrote:<br>
> Our VPX design uses separate reference clock source, which is Si52111-B5 (No<br>
> spread), instead of common ref clock from CPU.<br>
> Now The system is unstable. Reading PCIE configuration space is unstable<br>
> too. (If we add some fly wire to make it work with common ref clock, the<br>
> system becomes stable.)<br>
><br>
> (abstracted from PCIe spec: 12 Slot Clock Configuration - This bit indicates<br>
> that the<br>
> component uses the same physical reference clock that the<br>
> platform provides on the connector. If the device uses an<br>
> independent clock irrespective of the presence of a reference<br>
> clock on the connector, this bit must be clear.<br>
> For a multi-Function device, each Function must report the<br>
> same value for this bit.)<br>
><br>
> Based on my understanding, the BIOS need to read bit "Slot Clock<br>
> Configurationclear" to see if<br>
> separate ref clock is used. BIOS then write bit "Common Clock<br>
> Configuration".<br>
><br>
> On our board, the bit "Slot Clock Configuration" is always 1, which I assume<br>
> should be 0.<br>
><br>
> My question is, how the hardware affect the bit "Slot Clock Configuration"?<br>
> How do we need to design our board to make the bit "Slot Clock<br>
> Configuration" be 0?<br>
><br>
> Thanks.<br>
><br>
> Zheng<br>
><br>
><br>
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