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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">HI Andy,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">RCC-VE dev board from ADI has also memory down. It may help to compare. But unfortunately, schematics are not available.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Regards,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Patrick Agrain<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span lang="FR" style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">De :</span></b><span lang="FR" style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> coreboot [mailto:coreboot-bounces@coreboot.org]
<b>De la part de</b> Andy Knowles<br>
<b>Envoyé :</b> lundi 23 janvier 2017 11:00<br>
<b>À :</b> Zoran Stojsavljevic<br>
<b>Cc :</b> coreboot@coreboot.org<br>
<b>Objet :</b> Re: [coreboot] Rangeley FSP reports "Err[24]: GetSet Value exceeds limits" during memory init<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><span lang="EN-AU" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Hi Zoran,<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-AU" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-AU" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Thanks for responding. I have built and tested coreboot+FSP (using BCT) on a DIMM based Rangeley board without issues. Unfortunately I don’t have
any other memory down based boards to test on except our own prototype. But I can try to fake memory down on the DIMM board and see if it still works.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-AU" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-AU" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">I’m waiting on a debug FSP from Intel, hopefully that will narrow down the problem on our prototype hardware.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-AU" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-AU" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Regards,<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-AU" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Andy<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-AU" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><a name="_MailEndCompose"></a><span lang="EN-AU" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal" style="margin-bottom:12.0pt"><b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> Zoran Stojsavljevic [<a href="mailto:zoran.stojsavljevic@gmail.com">mailto:zoran.stojsavljevic@gmail.com</a>]
<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU">Hello Andy,<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU">I would advise to you to try the same coreboot with DIMM or SIMM INTEL Rangeley based CRB, and see if this does work, for some reason? Couple of experiments more with different CRBs with different memory configurations
would not make too much headaches, don't you think?<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU">If you do not use BCT tool, the following is true. You should use Binary Configuration TOOL (BCT) to change some configuration parameters for Rangeley (you should have in Rangeley FSP package also included BCT)!<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU"><o:p> </o:p></span></p>
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<p class="MsoNormal"><i><u><span lang="EN-AU">As previously discussed, even though Intel FSP is a binary file, it needs a provision to customize its internal states and features; therefore, it has reserved a data region inside the binary for customization.
The data area also contains a couple of platform-specific parameters that Intel FSP would otherwise have no knowledge about, or would initialize the board with default values. The Boot Setting File (BSF) plays an important role for this purpose. It is basically
a text file that contains firmware internal settings associated with the board; for example, the SMBUS (System Management Bus) address of a SPD (Serial Presence Detect) ROM on a DIMM (Dual Inline Memory Module) is one of the data in the BSF.</span></u></i><span lang="EN-AU"><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU"><o:p> </o:p></span></p>
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<p class="MsoNormal"><i><u><span lang="EN-AU">$gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1 1 byte $_DEFAULT_ = 0xA0</span></u></i><span lang="EN-AU"><o:p></o:p></span></p>
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<p class="MsoNormal"><i><u><span lang="EN-AU">$gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2 1 byte $_DEFAULT_ = 0xA2</span></u></i><span lang="EN-AU"><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU"><o:p> </o:p></span></p>
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<p class="MsoNormal"><i><u><span lang="EN-AU">The data in BSF is represented in a GUI-based tool, which allows developers to visualize the meaning of each component in BSF. With the GUI and BSF, it is collectively called a Binary Configuration Tool (BCT). There
are three versions of BCT: one runs under Windows, one runs under Linux, and the third is a command-line option under Linux.</span></u></i><span lang="EN-AU"><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU">Please, search for the book called: </span><b><span lang="EN-AU" style="font-size:13.0pt">Embedded Firmware Solutions [describing INTEL FSP]...</span></b><span lang="EN-AU"><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU" style="font-size:9.5pt"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU" style="font-size:9.5pt">And search for Chapter 3. There, everything is explicitly well explained/organized.<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU" style="font-size:9.5pt"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU" style="font-size:9.5pt">Hope this helps,<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU" style="font-size:9.5pt">Zoran</span><span lang="EN-AU">
<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-AU"><o:p> </o:p></span></p>
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