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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Hello Andy,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">We were also facing such an issue when developing our Rangeley-based CPU board (with DIMM modules).<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">This message was due to a wrong polarization on the DATA_MASK pin.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">The pb with this message is that it is displayed in every case of failure during the DDR test.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">A good way to reduce the possibility is to ask your Intel contact to provide you with a verbose FSP. That way, you may see at which part of the test you get
the failure.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Hope it helps.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Best regards,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Patrick Agrain<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span lang="FR" style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">De :</span></b><span lang="FR" style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> coreboot [mailto:coreboot-bounces@coreboot.org]
<b>De la part de</b> Zoran Stojsavljevic<br>
<b>Envoyé :</b> dimanche 22 janvier 2017 14:15<br>
<b>À :</b> Andy Knowles<br>
<b>Cc :</b> coreboot@coreboot.org<br>
<b>Objet :</b> Re: [coreboot] Rangeley FSP reports "Err[24]: GetSet Value exceeds limits" during memory init<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Hello Andy,<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">I would advise to you to try the same coreboot with DIMM or SIMM INTEL Rangeley based CRB, and see if this does work, for some reason? Couple of experiments more with different CRBs with different memory configurations would not make too
much headaches, don't you think?<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">If you do not use BCT tool, the following is true. You should use Binary Configuration TOOL (BCT) to change some configuration parameters for Rangeley (you should have in Rangeley FSP package also included BCT)!<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><i><u>As previously discussed, even though Intel FSP is a binary file, it needs a provision to customize its internal states and features; therefore, it has reserved a data region inside the binary for customization. The data area also
contains a couple of platform-specific parameters that Intel FSP would otherwise have no knowledge about, or would initialize the board with default values. The Boot Setting File (BSF) plays an important role for this purpose. It is basically a text file that
contains firmware internal settings associated with the board; for example, the SMBUS (System Management Bus) address of a SPD (Serial Presence Detect) ROM on a DIMM (Dual Inline Memory Module) is one of the data in the BSF.</u></i><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><i><u>$gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1 1 byte $_DEFAULT_ = 0xA0</u></i><o:p></o:p></p>
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<p class="MsoNormal"><i><u>$gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2 1 byte $_DEFAULT_ = 0xA2</u></i><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><i><u>The data in BSF is represented in a GUI-based tool, which allows developers to visualize the meaning of each component in BSF. With the GUI and BSF, it is collectively called a Binary Configuration Tool (BCT). There are three versions
of BCT: one runs under Windows, one runs under Linux, and the third is a command-line option under Linux.</u></i><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Please, search for the book called: <b><span style="font-size:13.0pt">Embedded Firmware Solutions [describing INTEL FSP]...</span></b><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.5pt"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.5pt">And search for Chapter 3. There, everything is explicitly well explained/organized.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.5pt"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.5pt">Hope this helps,<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.5pt">Zoran<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Fri, Jan 20, 2017 at 1:47 PM, Andy Knowles <<a href="mailto:aknowles@gallleonec.onmicrosoft.com" target="_blank">aknowles@gallleonec.onmicrosoft.com</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-AU">I’m trying to bring up an Intel Rangeley based prototype board using coreboot and Intel FSP. During FspInitEntry, FSP prints:<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-AU"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-AU">Err[24]: GetSet Value exceeds limits<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-AU"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-AU">to serial debug and halts. Does anyone know what this means?<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-AU"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-AU">I’m using the Memory Down option in the FSP and filling in the MEM_DOWN_DIMM_CONFIG structure in mainboard/…/romstage.c<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-AU">I can see that the FSP is reading and validating this structure, as changing the ram speed has an effect on memory clock frequency, and if I put in invalid values
the FSP will complain. I’ve tried reducing memory speed, disabling ECC, disabling channel 1 but I always get the same error.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-AU"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-AU">Does anyone else have any experience with Memory Down on Rangeley?<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-AU" style="color:#888888"> <o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span lang="EN-AU" style="color:#888888">Andy Knowles<o:p></o:p></span></p>
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