<div dir="ltr">Hello Stefan,<div><br></div><div>Let me ask you for some other stuff, since I would like to put what I wrote initially to hold (sleep state, for now).</div><div><br></div><div>You wrote: <u><span style="font-size:12.8px">The </span><span style="font-size:12.8px">official specs are not trustworthy IMHO and cpuid(1) and /proc/cpuinfo </span></u><u><span style="font-size:12.8px">show the same physical address width of 36 bits (which would indicate a </span></u><u><span style="font-size:12.8px">maximum of 64 GB).</span></u></div><div><i><span style="font-size:12.8px"><br></span></i></div><div><span style="font-size:12.8px">Question to you: are you dealing with i686 kernel, (32 bit)? It seems to me that you have Nehalem which complies in IA32 with PAE HW extension, don't you?!</span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px">What is PAE? Here: <a href="https://en.wikipedia.org/wiki/Physical_Address_Extension">https://en.wikipedia.org/wiki/Physical_Address_Extension</a></span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="color:rgb(37,37,37);font-family:sans-serif;font-size:14px">In </span><a href="https://en.wikipedia.org/wiki/Computing" title="Computing" style="text-decoration:none;color:rgb(11,0,128);background-image:none;background-position:initial;background-size:initial;background-repeat:initial;background-origin:initial;background-clip:initial;font-family:sans-serif;font-size:14px">computing</a><span style="color:rgb(37,37,37);font-family:sans-serif;font-size:14px">, </span><b style="color:rgb(37,37,37);font-family:sans-serif;font-size:14px">Physical Address Extension</b><span style="color:rgb(37,37,37);font-family:sans-serif;font-size:14px"> (</span><b style="color:rgb(37,37,37);font-family:sans-serif;font-size:14px">PAE</b><span style="color:rgb(37,37,37);font-family:sans-serif;font-size:14px">), sometimes referred to as </span><b style="color:rgb(37,37,37);font-family:sans-serif;font-size:14px">Page Address Extension</b><span style="color:rgb(37,37,37);font-family:sans-serif;font-size:14px">,</span><span style="color:rgb(37,37,37);font-family:sans-serif;font-size:14px"> is a memory management feature for the </span><a href="https://en.wikipedia.org/wiki/IA-32" title="IA-32" style="text-decoration:none;color:rgb(11,0,128);background-image:none;background-position:initial;background-size:initial;background-repeat:initial;background-origin:initial;background-clip:initial;font-family:sans-serif;font-size:14px">IA-32</a><span style="font-family:sans-serif;font-size:14px"><font color="#252525"> architecture. </font><b><i><u><font color="#ff0000">PAE was first introduced in the </font></u></i></b></span><b><i><u><font color="#ff0000"><a href="https://en.wikipedia.org/wiki/Pentium_Pro" title="Pentium Pro" style="background-image:none;background-position:initial;background-size:initial;background-repeat:initial;background-origin:initial;background-clip:initial;font-family:sans-serif;font-size:14px">Pentium Pro</a><span style="font-family:sans-serif;font-size:14px">. It defines a </span><a href="https://en.wikipedia.org/wiki/Page_table" title="Page table" style="background-image:none;background-position:initial;background-size:initial;background-repeat:initial;background-origin:initial;background-clip:initial;font-family:sans-serif;font-size:14px">page table</a><span style="font-family:sans-serif;font-size:14px"> hierarchy of three levels, with table entries of 64 bits each instead of 32, allowing these CPUs to access a physical </span><a href="https://en.wikipedia.org/wiki/Address_space" title="Address space" style="background-image:none;background-position:initial;background-size:initial;background-repeat:initial;background-origin:initial;background-clip:initial;font-family:sans-serif;font-size:14px">address space</a><span style="font-family:sans-serif;font-size:14px"> larger than 4 </span><a href="https://en.wikipedia.org/wiki/Gigabyte" title="Gigabyte" style="background-image:none;background-position:initial;background-size:initial;background-repeat:initial;background-origin:initial;background-clip:initial;font-family:sans-serif;font-size:14px">gigabytes</a><span style="font-family:sans-serif;font-size:14px"> (2</span><sup style="line-height:1;font-size:11.2px;font-family:sans-serif">32</sup></font></u></i></b><span style="font-family:sans-serif;font-size:14px"><b><i><u><font color="#ff0000"> bytes)</font></u></i></b><font color="#252525">.</font></span><span style="font-size:12.8px"><br></span></div><div><span style="font-family:sans-serif;font-size:14px"><font color="#252525"><br></font></span></div><div><span style="font-family:sans-serif;font-size:14px"><font color="#252525">This is very important -> </font></span><u><i><span style="color:rgb(37,37,37);font-family:sans-serif;font-size:14px">Enabling PAE (by setting bit 5, </span><code style="font-family:monospace,courier;color:rgb(0,0,0);background-color:rgb(248,249,250);border:1px solid rgb(234,236,240);border-radius:2px;padding:1px 4px;font-size:14px">PAE</code><span style="color:rgb(37,37,37);font-family:sans-serif;font-size:14px">, of the system register </span><code style="font-family:monospace,courier;color:rgb(0,0,0);background-color:rgb(248,249,250);border:1px solid rgb(234,236,240);border-radius:2px;padding:1px 4px;font-size:14px">CR4</code><span style="color:rgb(37,37,37);font-family:sans-serif;font-size:14px">) causes major changes to this scheme...</span></i></u></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px">Thank you,</span></div><div><span style="font-size:12.8px">Zoran</span></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Sat, Jan 28, 2017 at 3:10 PM, Stefan Tauner <span dir="ltr"><<a href="mailto:stefan.tauner@alumni.tuwien.ac.at" target="_blank">stefan.tauner@alumni.tuwien.ac.at</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">On Sun, 22 Jan 2017 12:33:08 +0100<br>
Zoran Stojsavljevic <<a href="mailto:zoran.stojsavljevic@gmail.com">zoran.stojsavljevic@gmail.com</a><wbr>> wrote:<br>
<br>
> Hello Stefan,<br>
><br>
> In addition what Charlotte wrote to you, I would advise you the following<br>
> (as general approach for mem problems):<br>
> [1] Please, for testing the memory, use secondary Coreboot payload called<br>
> MEMTEST:<br>
> [user@localhost coreboot]$ cat .config | grep MEMTEST<br>
> CONFIG_MEMTEST_SECONDARY_<wbr>PAYLOAD=y<br>
> CONFIG_MEMTEST_STABLE=y<br>
> # CONFIG_MEMTEST_MASTER is not set<br>
><br>
> Instead going to SeaBIOS or GRUB2 as payloads. This memtest86+ could (my<br>
> best guess) show to you what is wrong with your memory configuration.<br>
><br>
> [2] You can also (since you are able to in some cases go to Linux) stop in<br>
> GRUB2, after installing from Linux memtest86+ package into the GRUB2 boot<br>
> options (this can also help too, my best guess).<br>
><br>
> (extra advise: if you use legacy/CSM ON, which is in Coreboot in 99.999%<br>
> cases used, it would be much easier for you to deal with memtest86+)<br>
<br>
</span>Hi Zoran,<br>
<br>
I am not exactly sure what you are trying to convey. I mentioned<br>
that memtest did lock up after some seconds with the vendor firmware in<br>
my previous mail. Of course it's the first thing to try when memory<br>
problems arise - I just tried to boot Linux to retrieve the e820 map<br>
because Nico requested it on IRC. I presume that using memtest as<br>
primary or secondary payload or booted from GRUB2 would not produce<br>
different results (unless the binaries are different of course), no?<br>
<div class="HOEnZb"><div class="h5"><br>
--<br>
Kind regards/Mit freundlichen Grüßen, Stefan Tauner<br>
</div></div></blockquote></div><br></div>