<div dir="ltr">I see... It seems that I got the idea. This one I freely share with the community!<div><br></div><div>Some MSRs, or some PCIe registers must be enabled on SoC (namely, integrated in PCH), and they must be enabled at BSP (BIOS/Coreboot) time.<div><br></div><div>You need to ask INTEL IOTG support to tell to you which ones, so Coreboot people can get the idea how and where to implement this SVID enabling (MSR or PCIe space) addendum, in order to enable INTEL user space power tools in Linux.</div><div><br></div><div>I do NOT know which ones (not knowing answer to this question, in particular, and lazy to investigate), in contrary to previous problem with enabling Nehalem DDRs. ;-)</div><div><br></div><div>Zoran</div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Feb 1, 2017 at 10:23 AM, Mayuri Tendulkar <span dir="ltr"><<a href="mailto:mayuri.tendulkar@aricent.com" target="_blank">mayuri.tendulkar@aricent.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div lang="EN-IN" link="blue" vlink="purple">
<div class="m_1488677531184522240WordSection1">
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">We want to access this from Linux kernel Ubuntu 14.04.5<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Zoran Stojsavljevic [mailto:<a href="mailto:zoran.stojsavljevic@gmail.com" target="_blank">zoran.stojsavljevic@<wbr>gmail.com</a>]
<br>
<b>Sent:</b> 01 February 2017 14:33<br>
<b>To:</b> Mayuri Tendulkar <<a href="mailto:mayuri.tendulkar@aricent.com" target="_blank">mayuri.tendulkar@aricent.com</a>><br>
<b>Cc:</b> coreboot <<a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a>><br>
<b>Subject:</b> Re: [coreboot] SVID interface support on Intel Baytrail<u></u><u></u></span></p><div><div class="h5">
<p class="MsoNormal"><u></u> <u></u></p>
<div>
<p class="MsoNormal"><span style="font-size:9.5pt">> In our design, we are using SVID interface on Intel Baytrail for accessing PMIC.</span><u></u><u></u></p>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:9.5pt">From where? BIOS? Linux kernel? Which SW package?</span><u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:9.5pt">What about EC in these equations?</span><u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:9.5pt">Zoran</span><u></u><u></u></p>
</div>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
<div>
<p class="MsoNormal">On Wed, Feb 1, 2017 at 9:26 AM, Mayuri Tendulkar <<a href="mailto:mayuri.tendulkar@aricent.com" target="_blank">mayuri.tendulkar@aricent.com</a>> wrote:<u></u><u></u></p>
<blockquote style="border:none;border-left:solid #cccccc 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-right:0cm">
<div>
<div>
<p class="MsoNormal">Hi
<u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<p class="MsoNormal">In our design, we are using SVID interface on Intel Baytrail for accessing PMIC.<u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<p class="MsoNormal">But in coreboot, we don’t see any support enabled for this interface for Baytrail.<u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<p class="MsoNormal">Does anybody have idea how to access this interface?<u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<p class="MsoNormal">Regards<u></u><u></u></p>
<p class="MsoNormal">Mayuri<u></u><u></u></p>
</div>
<p class="MsoNormal">"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose
other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing
the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
<u></u><u></u></p>
</div>
<p class="MsoNormal"><br>
--<br>
coreboot mailing list: <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br>
<a href="https://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">https://www.coreboot.org/<wbr>mailman/listinfo/coreboot</a><u></u><u></u></p>
</blockquote>
</div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
</div></div></div><div><div class="h5">
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what
it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this
message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
</div></div></div>
</blockquote></div><br></div>