<div dir="ltr"><span style="color:rgb(31,73,125);font-family:calibri,sans-serif;font-size:14.6667px">> As for our prototype, we got it to boot with one memory channel while ‘hot’. We’re working with Intel to narrow it down,</span><div><span style="color:rgb(31,73,125);font-family:calibri,sans-serif;font-size:14.6667px">> but it looks like a marginal trace length issue. The verbose FSP tells us we are having issues during Command Clock Training.</span><br></div><div><span style="color:rgb(31,73,125);font-family:calibri,sans-serif;font-size:14.6667px"><br></span></div><div><font color="#1f497d" face="calibri, sans-serif"><span style="font-size:14.6667px">As I recall, INTEL provides HW PCB evaluation support for custom platforms, for VIP IOTG customers. There is also INTEL trace length calculation tool, for each family of ATOM/CORE. Important things to note (area: board HW design and verification), Andy. <img src="cid:ii_159ff7ba7e7a6575" alt="Inline image 1" width="16" height="16"></span></font></div><div><font color="#1f497d" face="calibri, sans-serif"><span style="font-size:14.6667px"><br></span></font></div><div><font color="#1f497d" face="calibri, sans-serif"><span style="font-size:14.6667px">Since I also recall that Rangeley has some Gen.3 SATA support (2 ports), I also will advise you to check/pay attention to these, during Lane Clock training/SATA 3 Protocol training... Just in case.</span></font></div><div><font color="#1f497d" face="calibri, sans-serif"><span style="font-size:14.6667px"><br></span></font></div><div><font color="#1f497d" face="calibri, sans-serif"><span style="font-size:14.6667px">Good Luck,</span></font></div><div><font color="#1f497d" face="calibri, sans-serif"><span style="font-size:14.6667px">Zoran</span></font></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Feb 2, 2017 at 2:28 PM, Andy Knowles <span dir="ltr"><<a href="mailto:aknowles@galleonec.com" target="_blank">aknowles@galleonec.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">A follow-up, for posterity:<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">I got the RCC-DFF from ADI to boot using the memory down option. To do this, I enabled Memory Down in the FSP (via BCT) and also changed
all of the SPD SMBus Addresses to 0xff, to make sure the EEPROM wasn’t being used. Booting with this FSP I get an expected “No DIMMs Present” error.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">I then modified src/mainboard/adi/rcc-dff/<wbr>romstage.c as attached, specifying the SPD data from the Kingston datasheet and one populated
DIMM on channel 0.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">The RCC-DFF then booted normally.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">As for our prototype, we got it to boot with one memory channel while ‘hot’. We’re working with Intel to narrow it down, but it looks
like a marginal trace length issue. The verbose FSP tells us we are having issues during Command Clock Training.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Thanks again for responses!<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Andy<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><a name="m_-2632590435558212399__MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></a></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif"> coreboot [mailto:<a href="mailto:coreboot-bounces@coreboot.org" target="_blank">coreboot-bounces@<wbr>coreboot.org</a>]
<b>On Behalf Of </b>Andy Knowles<br>
<b>Sent:</b> Monday, 23 January 2017 11:55<br>
<b>To:</b> Agrain Patrick <<a href="mailto:patrick.agrain@al-enterprise.com" target="_blank">patrick.agrain@al-enterprise.<wbr>com</a>><br>
<b>Cc:</b> <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br>
<b>Subject:</b> Re: [coreboot] Rangeley FSP reports "Err[24]: GetSet Value exceeds limits" during memory init<u></u><u></u></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Hi Patrick,<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">I have an RCC-DFF from ADI. The memory is soldered down, but from their BIOS source it seems they aren’t using the FSP memory down
option, so I suspect they have an EEPROM on the board with SPD data pretending to be a DIMM. I’m going to try booting it with memory down set in FSP and SPD data in coreboot instead.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Thanks,<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Andy<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Agrain Patrick [</span><a href="mailto:patrick.agrain@al-enterprise.com" target="_blank"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">mailto:patrick.agrain@al-<wbr>enterprise.com</span></a><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">]
<u></u><u></u></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">HI Andy,<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">RCC-VE dev board from ADI has also memory down. It may help to compare. But unfortunately, schematics are not available.<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Regards,<u></u><u></u></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Patrick Agrain</span><span lang="EN-US">
</span><u></u><u></u></p>
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