Terminal ready coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e06684c FIDVID on BSP, APIC_id: 00 BSP fid = 0 get_boot_apic_id: using 0 as APIC ID for node 0, core 0 get_boot_apic_id: using 1 as APIC ID for node 0, core 1 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 3 as APIC ID for node 0, core 3 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 5 as APIC ID for node 0, core 5 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 get_boot_apic_id: using 7 as APIC ID for node 0, core 7 get_boot_apic_id: using 8 as APIC ID for node 1, core 0 get_boot_apic_id: using 9 as APIC ID for node 1, core 1 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 11 as APIC ID for node 1, core 3 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 13 as APIC ID for node 1, core 5 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 get_boot_apic_id: using 15 as APIC ID for node 1, core 7 get_boot_apic_id: using 32 as APIC ID for node 2, core 0 get_boot_apic_id: using 33 as APIC ID for node 2, core 1 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 35 as APIC ID for node 2, core 3 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 37 as APIC ID for node 2, core 5 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 get_boot_apic_id: using 39 as APIC ID for node 2, core 7 get_boot_apic_id: using 40 as APIC ID for node 3, core 0 get_boot_apic_id: using 41 as APIC ID for node 3, core 1 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 43 as APIC ID for node 3, core 3 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 45 as APIC ID for node 3, core 5 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 get_boot_apic_id: using 47 as APIC ID for node 3, core 7 Wait for AP stage 1: ap_apicid = 1 readback = 1000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2 readback = 2000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 3 readback = 3000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 4 readback = 4000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 5 readback = 5000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 6 readback = 6000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 7 readback = 7000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 8 readback = 8000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 9 readback = 9000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = a readback = a000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = b readback = b000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = c readback = c000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = d readback = d000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = e readback = e000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = f readback = f000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 20 readback = 20000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 21 readback = 21000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 22 readback = 22000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 23 readback = 23000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 24 readback = 24000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 25 readback = 25000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 26 readback = 26000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 27 readback = 27000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 28 readback = 28000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 29 readback = 29000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2a readback = 2a000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2b readback = 2b000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2c readback = 2c000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2d readback = 2d000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2e readback = 2e000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2f readback = 2f000014 common_fid(packed) = 0 common_fid = 0 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e06684c sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode ...WARM RESET... coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0004 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode ...WARM RESET... coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0004 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start coreboot-4.5-964-gd96669e9db Sat Feb 11 13:58:51 UTC 2017 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d20,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0400 WARNING: Last reset was caused by fatal error / sync flood! CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 6bd40 size 318c CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2dd00 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 02 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 00 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 00 03 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 01 03 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 02 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 02 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 00 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 01 AMD_CB_EventNotify(): HARDWARE FAULT: HT_EVENT_HW_SYNCHFLOOD event class: 03 event: 4001 data: 03 03 03 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c000a6 0x3e025a07 End FIDVIDMSR 0xc0010071 0x52c000a6 0x3e025a07 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 Node 01 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601328 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000020 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c20 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 01 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 Thanks for using picocom picocom v1.7 port is : /dev/ttyS0 flowcontrol : none baudrate is : 115200 parity is : none databits are : 8 escape is : C-a local echo is : no noinit is : no noreset is : no nolock is : no send_cmd is : sz -vv receive_cmd is : rz -vv imap is : omap is : emap is : crcrlf,delbs,