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<div class="" style="word-wrap:break-word">Hi Kyösti,
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<div class="" style="orphans:2; widows:2">Yes, sorry about that! I’ve attached the patch against the source (last commit: <span class="" style="orphans:2; widows:2">021ec2819b2200eabbaca5b6873f7024c2bd9434). As reference, I’ve also attached the output of the
boot process (via the serial port).</span></div>
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<div class="" style="orphans:2; widows:2">With regards to the address I am writing to, I am writing to the range 0x200000 - 0x300000. I guess this may be in the L2 cache-as-RAM and thus not demonstrate the behavior I’m expecting..</div>
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<div class="" style="orphans:2; widows:2">Thanks again for your help,</div>
<div class="" style="orphans:2; widows:2">Berj</div>
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<div class="">On Mar 23, 2017, at 10:53 PM, Kyösti Mälkki <<a href="mailto:kyosti.malkki@gmail.com" class="">kyosti.malkki@gmail.com</a>> wrote:</div>
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<div class="x_gmail_quote">On Fri, Mar 24, 2017 at 2:15 AM, Berj K Chilingirian <span dir="ltr" class="">
<<a href="mailto:berjc@mit.edu" target="_blank" class="">berjc@mit.edu</a>></span> wrote:<br class="">
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<div class="" style="word-wrap:break-word">Hi,
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<div class="">I was hoping to get some advice/guidance on how to disable the automatic refresh of the DRAM during the ROM stage of coreboot.</div>
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<div class="">I am booting an ASUS F2A85-M motherboard with a AMD A6-5400k processor (Trinity core) using coreboot. The processor is initialized via the AGESA bootstrap protocol.</div>
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<div class="">I would like to use the <a href="https://github.com/coreboot/coreboot/tree/master/src/vendorcode/amd/agesa/f15tn" target="_blank" class="">AGESA software</a> in order to measure the retention time of DRAM cells (i.e. the time a DRAM cell holds
its value with refresh shut off). To do this, I must (1) run my code in cache-as-RAM mode because DRAM becomes unreliable without refresh and (2) have a way to switch DRAM refresh on/off from software. (1) is accomplished by running my code in the cache-as-RAM
phase of coreboot (i.e. the ROM stage). I am, however, unclear on how to accomplish (2) and I was hoping to receive some pointers/guidance on how to do this.</div>
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<div class="">The AGESA protocol seems to handle memory initialization in the <a href="https://github.com/coreboot/coreboot/blob/master/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitPost.c#L223" target="_blank" class="">AmdInitPost</a> phase, specifically
in <a href="https://github.com/coreboot/coreboot/blob/master/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c#L135" target="_blank" class="">AmdMemAuto</a> In reading this code I discovered a call with which one could disable/enable the auto-refresh
feature of the DRAM. Specifically,</div>
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<div class=""><span class="x_m_-800854182970406067Apple-tab-span" style="white-space:pre-wrap"></span><a href="https://github.com/coreboot/coreboot/blob/master/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnreg.c#L218" target="_blank" class="">MemNSetBitFieldNb</a> (NBPtr,
BFDisAutoRefresh, 1);</div>
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<div class="">where NBPtr is a pointer to a data structure representing the northbridge configuration and <a href="https://github.com/coreboot/coreboot/blob/master/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h#L365" target="_blank" class="">BFDisAutoRefresh</a> is
a bit field which can be set to 1 in order to disable auto-refresh of the DRAM (see <a href="http://support.amd.com/TechDocs/42300_15h_Mod_10h-1Fh_BKDG.pdf" target="_blank" class="">AMD BKDG</a>, page 344 on DisAutoRefresh).</div>
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<div class="">With this interface, I thought I could (1) write a value to memory (using movnti instruction to bypass the cache), (2) disable auto-refresh using MemNSetBitFieldNb, (3) wait some number of seconds, (4) enable auto-refresh using MemNSetBitFieldNb,
and (5) check whether the value has persisted over the given period of time. Unfortunately, I discovered that even after waiting 3 minutes, the value in DRAM persisted (contrary to what seems to be expected by the <a href="http://www.pdl.cmu.edu/PDL-FTP/NVM/dram-retention_isca13.pdf" target="_blank" class="">literature</a>).
Note that I perform this procedure inside the <a href="https://github.com/coreboot/coreboot/blob/master/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c#L285" target="_blank" class="">AmdMemAuto</a> procedure of the AGESA code once all memory initialization
tasks have completed and before teardown occurs.</div>
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<div class="">Worried that the processor may be caching the value, I decided to flush data at the address before disabling auto-refresh with the following interface provided by the AGESA codebase:</div>
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<div class="">Patch against the source is easier to diagnose for possible mistakes than verbal expression of what you believe you are doing. Eg. the address you write to makes a difference.<br class="">
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<div class="">Kyösti<br class="">
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