[flashrom] [PATCH] Add Nvidia nForce MCP6x/MCP7x series SPI flashing support

[Carl-Daniel Hailfinger]

On 17.06.2010 17:39, Johannes Sjölund wrote:
> I also applied the patch and tested. See the attached log.
>
> flashrom v0.9.2-r1049 on Linux 2.6.33-ARCH (x86_64), built with libpci 3.1.7, GCC 4.5.0 20100520 (prerelease), little endian
> flashrom is free software, get the source code at http://www.flashrom.org
>
> Calibrating delay loop... OS timer resolution is 1 usecs, 927M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1000 us, 10000 myus = 10003 us, 4 myus = 5 us, OK.
> Initializing internal programmer
> No coreboot table found.
> DMI string system-manufacturer: "MSI"
> DMI string system-product-name: "MS-7369"
> DMI string system-version: "1.0"
> DMI string baseboard-manufacturer: "MSI"
> DMI string baseboard-product-name: "MS-7369"
> DMI string baseboard-version: "1.0"
> DMI string chassis-type: "Desktop"
> Found chipset "NVIDIA MCP65", enabling flash write... chipset PCI ID is 10de:0441, This chipset is not really supported yet. Guesswork...
> ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0
> Guessed flash bus type is SPI
> Found SMBus device 10de:0446 at 00:01:1
> SPI BAR is at 0xfec80000, after clearing low bits BAR is at 0xfec80000
> SPI control is 0x0002, enable=0, idle=0
> Please send the output of "flashrom -V" to flashrom at flashrom.org to help us finish support for your chipset. Thanks.
> OK.
> This chipset supports the following protocols: SPI.
> [...]
> Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014
> Chip status register is 00
> Chip status register: Status Register Write Disable (SRWD) is not set
> Chip status register: Bit 6 is not set
> Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
> Chip status register: Bit 4 / Block Protect 2 (BP2) is not set
> Chip status register: Bit 3 / Block Protect 1 (BP1) is not set
> Chip status register: Bit 2 / Block Protect 0 (BP0) is not set
> Chip status register: Write Enable Latch (WEL) is not set
> Chip status register: Write In Progress (WIP/BUSY) is not set
> Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000.
> [...]
> No operations were specified.
>   

Thanks for the log and the testing.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/