[flashrom] [coreboot] gigabyte dual bios programming

[Qing Pei Wang]

i think the spi chips are wired to both south bridge and super I/O.
carl:
   i do not think that SB700 has this mechanism, it must be the time circuit
of this patent.
i find that before booting bios, there is several seconds delay after
powering up.

On Fri, Jul 16, 2010 at 3:17 PM, Andriy Gapon <avg at icyb.net.ua> wrote:

> on 15/07/2010 21:09 Carl-Daniel Hailfinger said the following:
> >
> > Did you know that SB700 (and later) has its own Dual BIOS mechanism? If
> > there is interest, I can help with implementing support for that feature
> > in flashrom.
>
> Does that mechanism require that flash chips are wired to the south bridge
> (handled by its SPI controller)?  Or is it a more generic mechanism?
>
> --
> Andriy Gapon
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



-- 
Wang Qing Pei
Phone: 86+13426369984
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