[SerialICE] rdmsr
nils
njacobs8 at hetnet.nl
Mon May 16 21:23:15 CEST 2011
You wrote:
> 4.5.2.83 MSR Lock Register
> 4.5.2.84 Real Time Stamp Counter Register
> MSR Address 00001908
>
> "Lock MSRs. The CPU CoreMSRs above 0xFFF (with the exception of the MSR_LOCK
> register itself) are locked when this bit reads back as 1. To unlock
> these MSRs, write the
> value 45524F434C494156h to this register (the byte string “VAILCORE”).
> Writing any
....
Thanks for the excellent explanation!
Nils.
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