Via early startup - 1) Fixed version sensing via EC - needed to enable I/O decoding for the special EC port 2) Moved the startup delay to exactly the required point, just before the first CMOS access 3) Restore a couple of registers in D17F7 that are killed during S3.
cpu/x86/pc/olpc/via/romreset.bth
cpu/x86/pc/olpc/via/startcominit.fth