AMD IMC

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Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!

AMD IMC

The AMD IMC register interface visible from PCI space is documented in the AMD reference guides. This page tries to cover everything else which is not documented elsewhere.

The embedded controller is an 8051 CPU most likely derived from SMSC LPC47N350 Data Sheet or any recent SMSC embedded controller core. As the 8051, it has 3 memory spaces. The SFR, internal RAM and external space where the hardware has specific registers mapped. The code is fetched from 16KB? region of flash the base address is set to 0xFFF20000 (in SB710).

Enabling/Disabling the IMC

The EC is turned on if the soft straps are set to on during the init of the southbridge, this is documented in the SB datasheet. To make it operational you will need to modify the strap bits and include the IMC firmware in the coreboot image. The 8051 reset vector is first instruction. The firmware itself contains a magic _AMD_IMC_C and you can check validateImcFirmware() how it works.

To check if IMC is active check if PCI 0:14.3 0x40 bit7 set.

Firmware

The IMC gets its firmware from the main system flash chip where coreboot/BIOS/EFI resides. Ruik has developed a minimal replacement firmware, it is available upon request.

SuperIO Register space

The IMC presents itself as an multifunction superIO device. You can read the sioport base in the following register PCI 14.3 0xa4 & ~0x1. The access pattern is same as for any other superio. The superiotool has some basic routines implemented. In general, there is a "password" to unlock the SIO part - 0x5a and lock it with 0xa5 again.

The known global registers:

Firmware commands

The firmware accepts variety of commands through the mailbox interface. The command is passed in 0x80 (SYS_TO_IMC) and data in 0x83 REG1, REG2 ... The format of the commands is: [fn in 0x80]: [data in REG1, REG2 ... ].

External memory (DPTR access)