Nvidia CK804 Porting Notes

The wiki is being retired!

Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!

This document does not (at present) attempt to be as complete as the AMD Geode Porting Guide, which has more general information.


There is no publicly available documentation on the CK804, the source (and, of course, reverse engineering) is your only hope.

Audio and Network

If your CK804 has an AC97 codec, or ethernet PHY connected to it, you'll probably want to define CK804_USE_ACI and CK804_USE_NIC respectively.

Without CK804_USE_ACI = 1, the audio driver will time out when attempting to communicate with the codec.

Interrupt Routing Registers

Please note that this is valid for MCP55 too.

Obtained via playing with these registers with setpci(8). Some information is still missing.

These routing registers are in the LPC bridge PCI configuration space (device 1, function 0).

Nibble values for routing registers:

Nibble APIC Pin
1h 23
2h 22
3h 16
4h 17
5h 5
6h 18
7h 7
8h 20
Ch 12
Dh 21
Eh 14
Fh 15


Bits Description
27:24 SATA at device 7, second port
23:20 SATA at device 8, second port
15:0 PCI IRQ mappings?


Bits Description
31:28 SATA at device 7, first port
27:24 SATA at device 8, first port
15:12 EHCI (device 2, function 1)


Bits Description
19:16 AC'97 audio (device 4, function 0)
11:8 NIC (device 10, function 0)
3:0 OHCI (device 2, function 0)

One thing to note is that interrupts on both ports of the SATA controllers should be routed to the same pin so that the device behaves the way the driver expects them to.

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