https://www.coreboot.org/api.php?action=feedcontributions&user=Phcoder&feedformat=atomcoreboot - User contributions [en]2024-03-19T06:22:39ZUser contributionsMediaWiki 1.40.0https://www.coreboot.org/index.php?title=User_talk:SamPabloKuper&diff=24719User talk:SamPabloKuper2017-03-18T18:19:13Z<p>Phcoder: Created page with "For X201: yes, when flashing externally everything is rewritable. Feel free to clarify."</p>
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<div>For X201: yes, when flashing externally everything is rewritable. Feel free to clarify.</div>Phcoderhttps://www.coreboot.org/index.php?title=Coreboot_conference_Bonn_2015&diff=17003Coreboot conference Bonn 20152015-10-06T23:14:16Z<p>Phcoder: /* Goodies */</p>
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<div></div>Phcoderhttps://www.coreboot.org/index.php?title=File:Tshirts.jpg&diff=16999File:Tshirts.jpg2015-10-06T20:34:37Z<p>Phcoder: Phcoder uploaded a new version of File:Tshirts.jpg</p>
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<div></div>Phcoderhttps://www.coreboot.org/index.php?title=File:Tshirts.jpg&diff=16998File:Tshirts.jpg2015-10-06T20:33:16Z<p>Phcoder: </p>
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<div></div>Phcoderhttps://www.coreboot.org/index.php?title=File:Cups3.jpg&diff=16997File:Cups3.jpg2015-10-06T20:29:47Z<p>Phcoder: </p>
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<div></div>Phcoderhttps://www.coreboot.org/index.php?title=File:Together.jpg&diff=16996File:Together.jpg2015-10-06T20:29:25Z<p>Phcoder: </p>
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<div></div>Phcoderhttps://www.coreboot.org/index.php?title=File:Plate2.jpg&diff=16995File:Plate2.jpg2015-10-06T20:29:19Z<p>Phcoder: </p>
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<div></div>Phcoderhttps://www.coreboot.org/index.php?title=File:Plate.jpg&diff=16994File:Plate.jpg2015-10-06T20:29:12Z<p>Phcoder: </p>
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<div></div>Phcoderhttps://www.coreboot.org/index.php?title=File:Magnets.jpg&diff=16993File:Magnets.jpg2015-10-06T20:28:56Z<p>Phcoder: </p>
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<div></div>Phcoderhttps://www.coreboot.org/index.php?title=File:Cups2.jpg&diff=16992File:Cups2.jpg2015-10-06T20:27:52Z<p>Phcoder: </p>
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<div></div>Phcoderhttps://www.coreboot.org/index.php?title=File:Cups.jpg&diff=16991File:Cups.jpg2015-10-06T20:27:47Z<p>Phcoder: </p>
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<div></div>Phcoderhttps://www.coreboot.org/index.php?title=File:Cap.jpg&diff=16990File:Cap.jpg2015-10-06T20:27:32Z<p>Phcoder: </p>
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<div></div>Phcoderhttps://www.coreboot.org/index.php?title=Coreboot_conference_Bonn_2015&diff=16989Coreboot conference Bonn 20152015-10-06T20:26:52Z<p>Phcoder: </p>
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<div></div>Phcoderhttps://www.coreboot.org/index.php?title=Motherboard_Porting_Guide&diff=16496Motherboard Porting Guide2015-05-29T21:35:11Z<p>Phcoder: </p>
<hr />
<div><br />
== Motherboard Porting Guide ==<br />
<br />
Please note that this is WIP work.<br />
<br />
== HOWTO to find a way ==<br />
<br />
* find a model and manufacturer of your mobo<br />
* download these tools:<br />
# git clone http://review.coreboot.org/p/coreboot<br />
# superiotool ( cd coreboot/util/superiotool ; make ; sudo make install )<br />
# inteltool ( cd coreboot/util/inteltool ; make ; sudo make install )<br />
# ectool ( cd coreboot/util/ectool ; make ; sudo make install )<br />
# dmidecode ( cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode co dmidecode )<br />
# msrtool ( cd coreboot/util/msrtool ; ./configure ; make ; sudo make install )<br />
# nvramtool ( cd coreboot/util/nvramtool ; make ; sudo make install )<br />
# flashrom ( svn co svn://coreboot.org/flashrom/trunk flashrom )<br />
* make and install them (make; sudo make install) - you need at least libpci/pciutils<br />
* check that your distro have this tools and install them:<br />
# lspci<br />
# dmesg<br />
# acpitool<br />
# lspnp <-- where do you actually get this? I couldn't find it anywhere.<br />
# lsusb<br />
# acpidump<br />
* # modprobe msr<br />
(this is for one of the steps below) <br />
* Do this commands '''as root''' (# remove for the easy copypasting):<br />
lspci -nnvvvxxxx > lspci.log 2>lspci.err.log<br />
lspnp -vv > lspnp.log 2>lspnp.err.log<br />
lsusb -vvv > lsusb.log 2>lsusb.err.log<br />
superiotool -deV > superiotool.log 2> superiotool.err.log<br />
inteltool -a > inteltool.log 2> inteltool.err.log<br />
ectool > ectool.log 2>ectool.err.log<br />
msrtool > msrtool.log 2>msrtool.err.log<br />
dmidecode > dmidecode.log 2>dmidecode.err.log<br />
biosdecode > biosdecode.log 2>biosdecode.err.log<br />
nvramtool -x > nvramtool.log 2>nvramtool.err.log<br />
dmesg > dmesg.log 2>dmesg.err.log<br />
flashrom -V -p internal:laptop=force_I_want_a_brick > flashrom_info.log 2>flashrom_info.err.log # this won't work on some vendor firmware<br />
flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > flashrom_read.log 2>flashrom_read.err.log # this won't work on some vendor firmware<br />
acpidump > acpidump.log 2>acpidump.err.log<br />
for x in /sys/class/sound/card0/hw*; do cat "$x/init_pin_configs" > pin_"$(basename "$x")"; done<br />
for x in /proc/asound/card0/codec#*; do cat "$x" > "$(basename "$x")"; done<br />
cat /proc/cpuinfo > cpuinfo.log 2>cpuinfo.err.log<br />
cat /proc/ioports > ioports.log 2>ioports.err.log<br />
cat /sys/class/input/input*/id/bustype > input_bustypes.log<br />
* Save all logs in safe place, and also rom.bin file. <br />
* Find what chip does your mobo use. The name of the chip is present in flashrom_info.log but is not always exact as some chips have several packaging variants (e.g. SOIC-16, SOIC-8 and TSOP). Consult [[http://flashrom.org/Technology]] for more info on possible chip formats. If possible make a high-resolution (600dpi or higher) scan of motherboard. Make a scan, not a photo as cameras typically don't have enough resolution to identify individual chips.<br />
* try to find information - what EC (if on laptop) or Super I/O chip (if any) is used in your mobo (may be some info in Service Manuals or Disassembly guides)<br />
* try to find your Super I/O / EC chip datasheet<br />
For laptop, additionally:<br />
* if you see that ectool return some fake stuff - like only 'FF' or '00' - so you have custom EC configuration, it's a hard work for support<br />
* if you see that ectool return looks like 'right' output - you have a big chances for support<br />
* you need to find from thease outputs Super I/O / EC chip name, or if not see this - disassembly your laptop<br />
<br />
=== Preparing recovery method ===<br />
<br />
Inevitably when you develop coreboot there will be unbootable builds and so you need a way to unbrick your machine after a failed image. There are several ways to do so. Main ones are:<br />
* In-system Programming. For more info consult [[http://flashrom.org/ISP]]<br />
* Hotswap. Consult [[http://flashrom.org/Technology]]<br />
In any case you have to locate the flash chip. Note the chipname from flashrom output. Teardown your system and find that chip. For how it usually looks like consult [[http://flashrom.org/Technology]]. If you have a scanner, do a high-resolution scan of your board, it may be useful later.<br />
<br />
=== Selecting Similar Board ===<br />
<br />
Most important criteria for finding similar board is chipset. Look at northbridge (device 0:0.0) and southbridge (LPC controller) in the lspci output. grep through coreboot tree to find how those chipsets are named, then grep for chipset name (case-insensitive) to find a board which uses it. If there are several of them, try to match (in order of decreasing importance) system type (desktop/laptop), SuperI/O and manufacturer.<br />
<br />
<br />
=== Adding a new board ===<br />
<br />
This is a two step process. If you mainboard already exists, skip to next section.<br />
<br />
==== Adding a new vendor to tree ====<br />
<br />
Create a directory in src/mainboard with the same name as vendor name. Add to src/mainboard/Kconfig<br />
new vendor entry, the rest of this example uses "foo" vendor.<br />
<br />
config VENDOR_FOO<br />
bool "Foo"<br />
<br />
Add also a include for new Kconfig file which holds the vendor motherboards in the vendor directory<br />
<br />
source "src/mainboard/foo/Kconfig"<br />
<br />
Create a src/mainboard/foo/Kconfig, copy from other vendor, and change the vendor name. Delete all mainboards. <br />
<br />
==== Adding a new motherboard to tree ====<br />
<br />
Asume that vendor name is foo and board type is bar. Add new configuration item in src/mainboard/foo/Kconfig<br />
<br />
config BOARD_FOO_BAR<br />
bool "BAR"<br />
<br />
Add include for board specific config:<br />
<br />
source "src/mainboard/foo/bar/Kconfig"<br />
<br />
==== Adjusting contents of new board directory ====<br />
<br />
Now copy your similar board and start adjusting. Your first stop is the Kconfig.<br />
<br />
* You need to change the condition in the first line to match your board:<br />
<br />
-if BOARD_VENDOR_BAR<br />
+if BOARD_VENDOR_BAZ<br />
<br />
* Change MAINBOARD_DIR and names<br />
* Change device options to match your config<br />
* Next stop go to mainboard.c and adjust GPIO config based on inteltool dump above.<br />
* Now you can flash the image and see what fails. <br />
* Later adjust hda_verb.h to get sound working properly (use initial pin dumps for reference)<br />
<br />
Look through the options and adjust <br />
<br />
Adjust Kconfig to fit the new vendor/model name and dont forget to change MAINBOARD_DIR and MAINBOARD_PART_NUMBER.</div>Phcoderhttps://www.coreboot.org/index.php?title=Motherboard_Porting_Guide&diff=16476Motherboard Porting Guide2015-05-28T09:49:22Z<p>Phcoder: Do not pollute logs with stderr</p>
<hr />
<div><br />
== Motherboard Porting Guide ==<br />
<br />
Please note that this is WIP work.<br />
<br />
== HOWTO to find a way ==<br />
<br />
* find a model and manufacturer of your mobo<br />
* download these tools:<br />
# git clone http://review.coreboot.org/p/coreboot<br />
# superiotool ( cd coreboot/util/superiotool ; make ; sudo make install )<br />
# inteltool ( cd coreboot/util/inteltool ; make ; sudo make install )<br />
# ectool ( cd coreboot/util/ectool ; make ; sudo make install )<br />
# dmidecode ( cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode co dmidecode )<br />
# msrtool ( cd coreboot/util/msrtool ; ./configure ; make ; sudo make install )<br />
# nvramtool ( cd coreboot/util/nvramtool ; make ; sudo make install )<br />
# flashrom ( svn co svn://coreboot.org/flashrom/trunk flashrom )<br />
* make and install them (make; sudo make install) - you need at least libpci/pciutils<br />
* check that your distro have this tools and install them:<br />
# lspci<br />
# dmesg<br />
# acpitool<br />
# lspnp <-- where do you actually get this? I couldn't find it anywhere.<br />
# lsusb<br />
# acpidump<br />
* # modprobe msr<br />
(this is for one of the steps below) <br />
* Do this commands (# remove for the easy copypasting):<br />
lspci -nnvvvxxxx > lspci.log 2>lspci.err.log<br />
lspnp -vv > lspnp.log 2>lspnp.err.log<br />
lsusb -vvv > lsusb.log 2>lsusb.err.log<br />
superiotool -deV > superiotool.log 2> superiotool.err.log<br />
inteltool -a > inteltool.log 2> inteltool.err.log<br />
ectool > ectool.log 2>ectool.err.log<br />
msrtool > msrtool.log 2>msrtool.err.log<br />
dmidecode > dmidecode.log 2>dmidecode.err.log<br />
biosdecode > biosdecode.log 2>biosdecode.err.log<br />
nvramtool -x > nvramtool.log 2>nvramtool.err.log<br />
dmesg > dmesg.log 2>dmesg.err.log<br />
flashrom -V -p internal:laptop=force_I_want_a_brick > flashrom_info.log 2>flashrom_info.err.log # this won't work on some vendor firmware<br />
flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > flashrom_read.log 2>flashrom_read.err.log # this won't work on some vendor firmware<br />
acpidump > acpidump.log 2>acpidump.err.log<br />
for x in /sys/class/sound/card0/hw*; do cat "$x/init_pin_configs" > pin_"$(basename "$x")"; done<br />
for x in /proc/asound/card0/codec#*; do cat "$x" > "$(basename "$x")"; done<br />
cat /proc/cpuinfo > cpuinfo.log 2>cpuinfo.err.log<br />
cat /proc/ioports > ioports.log 2>ioports.err.log<br />
* Save all logs in safe place, and also rom.bin file. <br />
* Find what chip does your mobo use. The name of the chip is present in flashrom_info.log but is not always exact as some chips have several packaging variants (e.g. SOIC-16, SOIC-8 and TSOP). Consult [[http://flashrom.org/Technology]] for more info on possible chip formats. If possible make a high-resolution (600dpi or higher) scan of motherboard. Make a scan, not a photo as cameras typically don't have enough resolution to identify individual chips.<br />
* try to find information - what EC (if on laptop) or Super I/O chip (if any) is used in your mobo (may be some info in Service Manuals or Disassembly guides)<br />
* try to find your Super I/O / EC chip datasheet<br />
For laptop, additionally:<br />
* if you see that ectool return some fake stuff - like only 'FF' or '00' - so you have custom EC configuration, it's a hard work for support<br />
* if you see that ectool return looks like 'right' output - you have a big chances for support<br />
* you need to find from thease outputs Super I/O / EC chip name, or if not see this - disassembly your laptop<br />
<br />
=== Preparing recovery method ===<br />
<br />
Inevitably when you develop coreboot there will be unbootable builds and so you need a way to unbrick your machine after a failed image. There are several ways to do so. Main ones are:<br />
* In-system Programming. For more info consult [[http://flashrom.org/ISP]]<br />
* Hotswap. Consult [[http://flashrom.org/Technology]]<br />
In any case you have to locate the flash chip. Note the chipname from flashrom output. Teardown your system and find that chip. For how it usually looks like consult [[http://flashrom.org/Technology]]. If you have a scanner, do a high-resolution scan of your board, it may be useful later.<br />
<br />
=== Selecting Similar Board ===<br />
<br />
Most important criteria for finding similar board is chipset. Look at northbridge (device 0:0.0) and southbridge (LPC controller) in the lspci output. grep through coreboot tree to find how those chipsets are named, then grep for chipset name (case-insensitive) to find a board which uses it. If there are several of them, try to match (in order of decreasing importance) system type (desktop/laptop), SuperI/O and manufacturer.<br />
<br />
<br />
=== Adding a new board ===<br />
<br />
This is a two step process. If you mainboard already exists, skip to next section.<br />
<br />
==== Adding a new vendor to tree ====<br />
<br />
Create a directory in src/mainboard with the same name as vendor name. Add to src/mainboard/Kconfig<br />
new vendor entry, the rest of this example uses "foo" vendor.<br />
<br />
config VENDOR_FOO<br />
bool "Foo"<br />
<br />
Add also a include for new Kconfig file which holds the vendor motherboards in the vendor directory<br />
<br />
source "src/mainboard/foo/Kconfig"<br />
<br />
Create a src/mainboard/foo/Kconfig, copy from other vendor, and change the vendor name. Delete all mainboards. <br />
<br />
==== Adding a new motherboard to tree ====<br />
<br />
Asume that vendor name is foo and board type is bar. Add new configuration item in src/mainboard/foo/Kconfig<br />
<br />
config BOARD_FOO_BAR<br />
bool "BAR"<br />
<br />
Add include for board specific config:<br />
<br />
source "src/mainboard/foo/bar/Kconfig"<br />
<br />
==== Adjusting contents of new board directory ====<br />
<br />
Now copy your similar board and start adjusting. Your first stop is the Kconfig.<br />
<br />
* You need to change the condition in the first line to match your board:<br />
<br />
-if BOARD_VENDOR_BAR<br />
+if BOARD_VENDOR_BAZ<br />
<br />
* Change MAINBOARD_DIR and names<br />
* Change device options to match your config<br />
* Next stop go to mainboard.c and adjust GPIO config based on inteltool dump above.<br />
* Now you can flash the image and see what fails. <br />
* Later adjust hda_verb.h to get sound working properly (use initial pin dumps for reference)<br />
<br />
Look through the options and adjust <br />
<br />
Adjust Kconfig to fit the new vendor/model name and dont forget to change MAINBOARD_DIR and MAINBOARD_PART_NUMBER.</div>Phcoderhttps://www.coreboot.org/index.php?title=Motherboard_Porting_Guide&diff=16473Motherboard Porting Guide2015-05-28T08:00:07Z<p>Phcoder: </p>
<hr />
<div><br />
== Motherboard Porting Guide ==<br />
<br />
Please note that this is WIP work.<br />
<br />
== HOWTO to find a way ==<br />
<br />
* find a model and manufacturer of your mobo<br />
* download these tools:<br />
# git clone http://review.coreboot.org/p/coreboot<br />
# superiotool ( cd coreboot/util/superiotool ; make ; sudo make install )<br />
# inteltool ( cd coreboot/util/inteltool ; make ; sudo make install )<br />
# ectool ( cd coreboot/util/ectool ; make ; sudo make install )<br />
# dmidecode ( cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode co dmidecode )<br />
# msrtool ( cd coreboot/util/msrtool ; ./configure ; make ; sudo make install )<br />
# nvramtool ( cd coreboot/util/nvramtool ; make ; sudo make install )<br />
# flashrom ( svn co svn://coreboot.org/flashrom/trunk flashrom )<br />
* make and install them (make; sudo make install) - you need at least libpci/pciutils<br />
* check that your distro have this tools and install them:<br />
# lspci<br />
# dmesg<br />
# acpitool<br />
# lspnp <-- where do you actually get this? I couldn't find it anywhere.<br />
# lsusb<br />
# acpidump<br />
* # modprobe msr<br />
(this is for one of the steps below) <br />
* Do this commands (# remove for the easy copypasting):<br />
lspci -nnvvvxxxx > lspci.log 2>&1<br />
lspnp -vv > lspnp.log 2>&1<br />
lsusb -vvv > lsusb.log 2>&1<br />
superiotool -deV > superiotool.log 2>&1<br />
inteltool -a > inteltool.log 2>&1<br />
ectool > ectool.log 2>&1<br />
msrtool > msrtool.log 2>&1<br />
dmidecode > dmidecode.log 2>&1<br />
biosdecode > biosdecode.log 2>&1<br />
nvramtool -x > nvramtool.log 2>&1<br />
dmesg > dmesg.log 2>&1<br />
flashrom -V -p internal:laptop=force_I_want_a_brick > flashrom_info.log 2>&1 # this won't work on some vendor firmware<br />
flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > flashrom_read.log 2>&1 # this won't work on some vendor firmware<br />
acpidump > acpidump.log 2>&1<br />
for x in /sys/class/sound/card0/hw*; do cat "$x/init_pin_configs" > pin_"$(basename "$x")" 2>&1; done<br />
for x in /proc/asound/card0/codec#*; do cat "$x" > "$(basename "$x")" 2>&1; done<br />
cat /proc/cpuinfo > cpuinfo.log 2>&1<br />
cat /proc/ioports > ioports.log<br />
* Save all logs in safe place, and also rom.bin file. <br />
* Find what chip does your mobo use. The name of the chip is present in flashrom_info.log but is not always exact as some chips have several packaging variants (e.g. SOIC-16, SOIC-8 and TSOP). Consult [[http://flashrom.org/Technology]] for more info on possible chip formats. If possible make a high-resolution (600dpi or higher) scan of motherboard. Make a scan, not a photo as cameras typically don't have enough resolution to identify individual chips.<br />
* try to find information - what EC (if on laptop) or Super I/O chip (if any) is used in your mobo (may be some info in Service Manuals or Disassembly guides)<br />
* try to find your Super I/O / EC chip datasheet<br />
For laptop, additionally:<br />
* if you see that ectool return some fake stuff - like only 'FF' or '00' - so you have custom EC configuration, it's a hard work for support<br />
* if you see that ectool return looks like 'right' output - you have a big chances for support<br />
* you need to find from thease outputs Super I/O / EC chip name, or if not see this - disassembly your laptop<br />
<br />
=== Preparing recovery method ===<br />
<br />
Inevitably when you develop coreboot there will be unbootable builds and so you need a way to unbrick your machine after a failed image. There are several ways to do so. Main ones are:<br />
* In-system Programming. For more info consult [[http://flashrom.org/ISP]]<br />
* Hotswap. Consult [[http://flashrom.org/Technology]]<br />
In any case you have to locate the flash chip. Note the chipname from flashrom output. Teardown your system and find that chip. For how it usually looks like consult [[http://flashrom.org/Technology]]. If you have a scanner, do a high-resolution scan of your board, it may be useful later.<br />
<br />
=== Selecting Similar Board ===<br />
<br />
Most important criteria for finding similar board is chipset. Look at northbridge (device 0:0.0) and southbridge (LPC controller) in the lspci output. grep through coreboot tree to find how those chipsets are named, then grep for chipset name (case-insensitive) to find a board which uses it. If there are several of them, try to match (in order of decreasing importance) system type (desktop/laptop), SuperI/O and manufacturer.<br />
<br />
<br />
=== Adding a new board ===<br />
<br />
This is a two step process. If you mainboard already exists, skip to next section.<br />
<br />
==== Adding a new vendor to tree ====<br />
<br />
Create a directory in src/mainboard with the same name as vendor name. Add to src/mainboard/Kconfig<br />
new vendor entry, the rest of this example uses "foo" vendor.<br />
<br />
config VENDOR_FOO<br />
bool "Foo"<br />
<br />
Add also a include for new Kconfig file which holds the vendor motherboards in the vendor directory<br />
<br />
source "src/mainboard/foo/Kconfig"<br />
<br />
Create a src/mainboard/foo/Kconfig, copy from other vendor, and change the vendor name. Delete all mainboards. <br />
<br />
==== Adding a new motherboard to tree ====<br />
<br />
Asume that vendor name is foo and board type is bar. Add new configuration item in src/mainboard/foo/Kconfig<br />
<br />
config BOARD_FOO_BAR<br />
bool "BAR"<br />
<br />
Add include for board specific config:<br />
<br />
source "src/mainboard/foo/bar/Kconfig"<br />
<br />
==== Adjusting contents of new board directory ====<br />
<br />
Now copy your similar board and start adjusting. Your first stop is the Kconfig.<br />
<br />
* You need to change the condition in the first line to match your board:<br />
<br />
-if BOARD_VENDOR_BAR<br />
+if BOARD_VENDOR_BAZ<br />
<br />
* Change MAINBOARD_DIR and names<br />
* Change device options to match your config<br />
* Next stop go to mainboard.c and adjust GPIO config based on inteltool dump above.<br />
* Now you can flash the image and see what fails. <br />
* Later adjust hda_verb.h to get sound working properly (use initial pin dumps for reference)<br />
<br />
Look through the options and adjust <br />
<br />
Adjust Kconfig to fit the new vendor/model name and dont forget to change MAINBOARD_DIR and MAINBOARD_PART_NUMBER.</div>Phcoderhttps://www.coreboot.org/index.php?title=Supported_Motherboards&diff=16467Supported Motherboards2015-05-27T21:47:09Z<p>Phcoder: </p>
<hr />
<div></div>Phcoderhttps://www.coreboot.org/index.php?title=Supported_Motherboards&diff=16466Supported Motherboards2015-05-27T21:40:29Z<p>Phcoder: </p>
<hr />
<div></div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x230&diff=15600Board:lenovo/x2302015-02-12T16:28:23Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X230 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
<br />
Tested:<br />
* S3 (Suspend to RAM)<br />
* RAM module combinations of 8G+8G, 8G+0, 0+8G, 4G+8G, 8G+4G, 8G+1G, 1G+0, 0+1G, 4G+0, 0+4G<br />
* USB (both 2.0 and 3.0 ports)<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplugging)<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reader.<br />
* Webcam<br />
* trackpoint<br />
* touchpad<br />
* Fn hotkeys<br />
* Keyboard backlight<br />
* Thinklight.<br />
* bluetooth<br />
* dock<br />
* msata (fixed in commit c8f54a1109072706e2fa091dc9ab4ad3eb057b42)<br />
* mini displayport<br />
* digitizer on x230t variant<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Code ==<br />
{{MergedIntoMaster}}<br />
<br />
== Flashing ==<br />
X230 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X230.jpg<br />
File:X230_chip.jpg<br />
File:X230_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. IF you've chosen CBFS_SIZE 4M or smaller that' the only chip you need to reflash.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed. If the file is 8M, you're flashing wrong chip, connect to the right one.<br />
<br />
* Write the flash. Since you have to write only top 4M, first split out those 4M:<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
* Use flashrom to flash top.rom.<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x220&diff=15085Board:lenovo/x2202015-01-06T21:03:49Z<p>Phcoder: /* Status */</p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X220 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
<br />
Tested (and works):<br />
* RAM module combinations of 4G+0, 4G+4G<br />
* S3 (Suspend to RAM)<br />
* digitizer on x220t variant<br />
* WLAN (first minipcie slot)<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* Fn hotkeys<br />
* Video (both internal and VGA, including native gfx init)<br />
* touchpad<br />
* battery indicator<br />
* Fingerprint reader.<br />
* Thermal management<br />
* Webcam<br />
* Expresscard slot (including hotplugging)<br />
* USB (all 3 ports)<br />
* bluetooth<br />
* SD card slot<br />
* LAN<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* WWAN<br />
* WLAN slot USB<br />
* Windows (through SeaBIOS; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* msata<br />
* displayport<br />
<br />
Not tested:<br />
* Thinklight (probably works).<br />
* dock (probably works)<br />
* USB 3.0 in some models (probably doesn't work)<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X220.jpg<br />
File:X220_chip.jpg<br />
File:X220_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed.<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x200&diff=14923Board:lenovo/x2002014-12-09T00:54:28Z<p>Phcoder: /* proprietary components status */</p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X200 port.<br />
Works:<br />
* USB<br />
* Audio (internal speakers, internal mic, headphones, external mic)<br />
* WLAN (first minipcie slot)<br />
* WWAN (second minipcie slot)<br />
* UWB (third minipcie slot)<br />
* SD card slot<br />
* LAN<br />
* Battery and AC indicator<br />
* Thermal<br />
* EEPROM<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* keyboard<br />
* Bluetooth<br />
* LID<br />
* Video (internal panel and VGA)<br />
* Hotkeys<br />
* Fingerprint reader.<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* suspend to RAM (S3)<br />
* Expresscard slot (including hotplug)<br />
* Wake on LID, wake on Fn.<br />
* Dock<br />
<br />
Untested:<br />
* Modem (probably works)<br />
* digitizer on x200t variant (probably doesn't work)<br />
<br />
<br />
== proprietary components status ==<br />
* CPU microcode<br />
* VGA option rom (optional): you need it if you want graphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) (optional) => can be removed by modifying the flash descriptor.<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
First flashing needs to be external. I use buspirate and pomona clip (SOIC-16)<br />
<br />
Flash in X200 is divided roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (6M-12K)<br />
* Rewriteable flash (2M-128K)<br />
* Locked bootblock (128K)<br />
<br />
<gallery><br />
File:X200.jpg<br />
File:X200_chip.jpg<br />
File:X200_clip.jpg<br />
</gallery><br />
<br />
Descriptor and bootblock are read-only. ME firmware is not readable.<br />
Rewriteable region can be rewritten easily with flashrom.<br />
<br />
For coreboot we need to preserve descriptor and ME firmware while overwriting<br />
rewriteable region and bootblock. To achieve this there are 2 ways:<br />
<br />
* External flasher.<br />
* Unlock bootblock<br />
<br />
For the first one proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the SPI chip which is under palmrest,<br />
around the position of trackpoint under protective layer. <br />
<br />
I recommend using SOIC-16 clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from ATX PSU.<br />
The pinout is as follows, the colors are buspirate colors<br />
=== front (display) ====<br />
NC - - MISO (black)<br />
ground (brown) - - CS (white)<br />
NC - - NC<br />
NC - - NC<br />
NC - - NC<br />
NC - - NC<br />
MOSI (gray) - - 3.3V (red)<br />
violet (SCLK) - - NC<br />
=== back (palmrest) ===<br />
<br />
* I wasn't able to eliminate interference in my setup (you may have better luck), so it worked only on 30kHz. Adding battery increased quality somewhat. Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media. Due to interference I reread it 10 times, 2 were corrupted.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=descriptor_me.bin count=6 bs=1M<br />
* Compile coreboot<br />
* Put descriptor and me back:<br />
dd if=descriptor_me.bin of=build/coreboot.rom bs=1M conv=notrunc<br />
* Flash the resulting build/coreboot.rom. If it fails due to interference, try again, and again. It took me ~10 times.</div>Phcoderhttps://www.coreboot.org/index.php?title=Supported_Motherboards&diff=14799Supported Motherboards2014-11-23T09:30:00Z<p>Phcoder: </p>
<hr />
<div></div>Phcoderhttps://www.coreboot.org/index.php?title=Supported_Motherboards&diff=14798Supported Motherboards2014-11-23T09:26:16Z<p>Phcoder: </p>
<hr />
<div></div>Phcoderhttps://www.coreboot.org/index.php?title=Motherboard_Porting_Guide&diff=14790Motherboard Porting Guide2014-11-22T10:01:23Z<p>Phcoder: /* HOWTO to find a way */</p>
<hr />
<div><br />
== Motherboard Porting Guide ==<br />
<br />
Please note that this is WIP work.<br />
<br />
== HOWTO to find a way ==<br />
<br />
* find a model and manufacturer of your mobo<br />
* download these tools:<br />
# git clone http://review.coreboot.org/p/coreboot<br />
# superiotool ( cd coreboot/util/superiotool ; make ; sudo make install )<br />
# inteltool ( cd coreboot/util/inteltool ; make ; sudo make install )<br />
# ectool ( cd coreboot/util/ectool ; make ; sudo make install )<br />
# dmidecode ( cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode co dmidecode )<br />
# msrtool ( cd coreboot/util/msrtool ; ./configure ; make ; sudo make install )<br />
# nvramtool ( cd coreboot/util/nvramtool ; make ; sudo make install )<br />
# flashrom ( svn co svn://coreboot.org/flashrom/trunk flashrom )<br />
* make and install them (make; sudo make install) - you need at least libpci/pciutils<br />
* check that your distro have this tools and install them:<br />
# lspci<br />
# dmesg<br />
# acpitool<br />
# lspnp<br />
# lsusb<br />
# acpidump<br />
* Do this commands (# remove for the easy copypasting):<br />
lspci -nnvvvxxxx > lspci.log<br />
lspnp -vv > lspnp.log<br />
lsusb -vvv > lsusb.log<br />
superiotool -deV > superiotool.log<br />
inteltool -a > inteltool.log<br />
ectool > ectool.log<br />
msrtool > msrtool.log<br />
dmidecode > dmidecode.log<br />
biosdecode > biosdecode.log<br />
nvramtool -x > nvramtool.log<br />
dmesg > dmesg.log<br />
flashrom -V -p internal:laptop=force_I_want_a_brick > flashrom_info.log<br />
flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > flashrom_read.log<br />
acpidump > acpidump.log<br />
for x in /sys/class/sound/card0/hw*; do cat "$x/init_pin_configs" > pin_"$(basename "$x")"; done<br />
for x in /proc/asound/card0/codec#*; do cat "$x" > "$(basename "$x")"; done<br />
cat /proc/cpuinfo > cpuinfo.log<br />
* Save all logs in safe place, and also rom.bin file. <br />
* Find what chip does your mobo use. The name of the chip is present in flashrom_info.log but is not always exact as some chips have several packaging variants (e.g. SOIC-16, SOIC-8 and TSOP). Consult [[http://flashrom.org/Technology]] for more info on possible chip formats. If possible make a high-resolution (600dpi or higher) scan of motherboard. Make a scan, not a photo as cameras typically don't have enough resolution to identify individual chips.<br />
* try to find information - what EC (if on laptop) or Super I/O chip (if any) is used in your mobo (may be some info in Service Manuals or Disassembly guides)<br />
* try to find your Super I/O / EC chip datasheet<br />
For laptop, additionally:<br />
* if you see that ectool return some fake staff - like only 'FF' or '00' - so you have custom EC configuration, it's a hard work for support<br />
* if you see that ectool return looks like 'right' output - you have a big chances for support<br />
* you need to find from thease outputs Super I/O / EC chip name, or if not see this - disassembly your laptop<br />
<br />
=== Preparing recovery method ===<br />
<br />
Inevitably when you develop coreboot there will be unbootable builds and so you need a way to unbrick your machine after a failed image. There are several ways to do so. Main ones are:<br />
* In-system Programming. For more info consult [[http://flashrom.org/ISP]]<br />
* Hotswap. Consult [[http://flashrom.org/Technology]]<br />
In any case you have to locate the flash chip. Note the chipname from flashrom output. Teardown your system and find that chip. For how it usually looks like consult [[http://flashrom.org/Technology]]. If you have a scanner, do a high-resolution scan of your board, it may be useful later.<br />
<br />
=== Selecting Similar Board ===<br />
<br />
Most important criteria for finding similar board is chipset. Look at northbridge (device 0:0.0) and southbridge (LPC controller) in the lspci output. grep through coreboot tree to find how those chipsets are named, then grep for chipset name (case-insensitive) to find a board which uses it. If there are several of them, try to match (in order of decreasing importance) system type (desktop/laptop), SuperI/O and manufacturer.<br />
<br />
<br />
=== Adding a new board ===<br />
<br />
This is a two step process. If you mainboard already exists, skip to next section.<br />
<br />
==== Adding a new vendor to tree ====<br />
<br />
Create a directory in src/mainboard with the same name as vendor name. Add to src/mainboard/Kconfig<br />
new vendor entry, the rest of this example uses "foo" vendor.<br />
<br />
config VENDOR_FOO<br />
bool "Foo"<br />
<br />
Add also a include for new Kconfig file which holds the vendor motherboards in the vendor directory<br />
<br />
source "src/mainboard/foo/Kconfig"<br />
<br />
Create a src/mainboard/foo/Kconfig, copy from other vendor, and change the vendor name. Delete all mainboards. <br />
<br />
==== Adding a new motherboard to tree ====<br />
<br />
Asume that vendor name is foo and board type is bar. Add new configuration item in src/mainboard/foo/Kconfig<br />
<br />
config BOARD_FOO_BAR<br />
bool "BAR"<br />
<br />
Add include for board specific config:<br />
<br />
source "src/mainboard/foo/bar/Kconfig"<br />
<br />
==== Adjusting contents of new board directory ====<br />
<br />
Now copy your similar board and start adjusting. Your first stop is the Kconfig.<br />
<br />
* You need to change the condition in the first line to match your board:<br />
<br />
-if BOARD_VENDOR_BAR<br />
+if BOARD_VENDOR_BAZ<br />
<br />
* Change MAINBOARD_DIR and names<br />
* Change device options to match your config<br />
* Next stop go to mainboard.c and adjust GPIO config based on inteltool dump above.<br />
* Now you can flash the image and see what fails. <br />
* Later adjust hda_verb.h to get sound working properly (use initial pin dumps for reference)<br />
<br />
Look through the options and adjust <br />
<br />
Adjust Kconfig to fit the new vendor/model name and dont forget to change MAINBOARD_DIR and MAINBOARD_PART_NUMBER.</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x220&diff=14773Board:lenovo/x2202014-11-19T20:11:57Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X220 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
<br />
Tested (and works):<br />
* RAM module combinations of 4G+0, 4G+4G<br />
* S3 (Suspend to RAM)<br />
* digitizer on x220t variant<br />
* WLAN (first minipcie slot)<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* Fn hotkeys<br />
* Video (both internal and VGA, including native gfx init)<br />
* touchpad<br />
* battery indicator<br />
* Fingerprint reader.<br />
* Thermal management<br />
* Webcam<br />
* Expresscard slot (including hotplugging)<br />
* USB (all 3 ports)<br />
* bluetooth<br />
* SD card slot<br />
* LAN<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* WWAN<br />
* WLAN slot USB<br />
* Windows (through SeaBIOS; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
<br />
Not tested:<br />
* Thinklight (probably works).<br />
* dock (probably works)<br />
* msata (probably works)<br />
* displayport (probably works)<br />
* USB 3.0 in some models (probably doesn't work)<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X220.jpg<br />
File:X220_chip.jpg<br />
File:X220_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed.<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x201&diff=14772Board:lenovo/x2012014-11-19T20:11:23Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X201 port.<br />
Issues:<br />
* Sometimes Gnome starts to think that battery is 10 time larger than real. Information from sysfs remains correct. Doesn't appear in newer gnome<br />
* Yellow USB port is not powered when computer is shut down or in S3.<br />
<br />
<br />
Tested:<br />
* RAM module combinations of 4G+4G, 4G, 2G+2G,4G+2G, 2G<br />
* suspend to RAM (S3)<br />
* USB<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplug)<br />
* Sound<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload & SeaBIOS-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reeader.<br />
* Webcam<br />
* Bluetooth<br />
* Digitizer on X201t variant.<br />
Not tested:<br />
* Modem<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* [[Intel_Management_Engine|ME(Management Engine)] => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Code ==<br />
{{MergedIntoMaster|review_url=http://review.coreboot.org/#/c/4514/}}<br />
<br />
== Flashing ==<br />
Flash in X201 is divided roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* Rewriteable flash (3M-96K)<br />
* Locked bootblock (96K)<br />
<br />
Descriptor and bootblock are read-only. ME firmware is not readable.<br />
Rewriteable region can be rewritten easily with flashrom.<br />
<br />
For coreboot we need to preserve descriptor and ME firmware while overwriting<br />
rewriteable region and bootblock. To achieve this there are 2 ways:<br />
<br />
* External flasher.<br />
* Unlock bootblock<br />
<br />
For the first one proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the SPI chip which is under keyboard,<br />
around the position of trackpoint under protective layer. <br />
{|<br />
|[[File:Lenovo-x201-bios-location-arrow.png |200px|thumb|center|found it!]]<br />
|[[File:X201_flash_location.png |200px|thumb|center|under the keyboard]]<br />
|}<br />
[[File:Spi-soic8-25L6445E.png|200px|thumb|right|The flash chip]]<br />
<br />
I recommend using SOIC-8 clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
The pinout is as follows, the colors are buspirate colors<br />
=== front (display) ====<br />
3.3V (red) N/C violet (CLK) MOSI (gray)<br />
| | | |<br />
dot | | | |<br />
CS (white) MISO (black) N/C ground (brown)<br />
=== back (touchpad) ===<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x201/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x201/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot. Remember to enable HAVE_IFD and HAVE_ME_BIN<br />
* Flash the resulting build/coreboot.rom<br />
<br />
The other way has never been successfully used but it's known that the<br />
locking mechanism is in bootblock itself and that original firmware has<br />
a way to update it as follows:<br />
* Flash an update of rewriteable region. On next boot bootblock parses the<br />
image and sees that it contains a compressed copy of new bootblock. That<br />
copy is uncompressed and flashed.<br />
A way to unlock the bootblock would be to modify a firmware update to have a<br />
copy of bootblock without protection. For this you need to compress the<br />
modified block to fit into original space. The compression used is Lempel-Ziv-<br />
Huffman variant. I've written a compressor for it but unfortunately it's not<br />
performant enough.<br />
<br />
<br />
===identify the regions===<br />
[root@x201 ~]# flashrom -r bios.bin -pinternal:laptop=force_I_want_a_brick<br />
flashrom v0.9.6.1-r1563 on Linux 3.10-1-grml-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found chipset "Intel QM57". Enabling flash write... WARNING: SPI Configuration Lockdown activated.<br />
FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only.<br />
FREG2: WARNING: Management Engine region (0x00003000-0x004fffff) is locked.<br />
PR0: WARNING: 0x007d0000-0x01ffffff is read-only.<br />
Please send a verbose log to flashrom@flashrom.org if this board is not listed on<br />
http://flashrom.org/Supported_hardware#Supported_mainboards yet.<br />
Writes have been disabled. You can enforce write support with the<br />
ich_spi_force programmer option, but it will most likely harm your hardware!<br />
If you force flashrom you will get no support if something breaks.<br />
OK.<br />
Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000.<br />
Reading flash... FAILED.<br />
<br />
it will print the ME regions:<br />
FREG2: WARNING: Management Engine region (0x00003000-0x004fffff) is locked.<br />
it will also print the chip:<br />
Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000.<br />
'''But as in this case, flashrom might misidentify the chip''', this output is from [[Media:Spi-soic8-25L6445E.png|this MX25L6445E]]<br />
<br />
visually verify your chip's part number and find an [http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf appropriate datasheet ]<br />
<br />
=>verify that its voltage matches with the programmer voltage...<br />
* Then man flashrom says:<br />
-l, --layout <file><br />
Read ROM layout from <file>.<br />
<br />
flashrom supports ROM layouts. This allows you to flash<br />
certain parts of the flash chip only. A ROM layout file contains multiple lines<br />
with the following syntax:<br />
<br />
startaddr:endaddr imagename<br />
<br />
startaddr and endaddr are hexadecimal addresses within the ROM<br />
file and do not refer to any physical address. Please note that using a 0x<br />
prefix for those hexadecimal numbers is not necessary, but you can't<br />
specify decimal/octal numbers. imagename is an arbitrary name for the<br />
region/image from startaddr to endaddr (both addresses included).<br />
<br />
Example:<br />
<br />
00000000:00008fff gfxrom<br />
00009000:0003ffff normal<br />
00040000:0007ffff fallback<br />
<br />
If you only want to update the image named normal in a ROM based on the layout above, run<br />
<br />
flashrom -p prog --layout rom.layout --image normal -w some.rom<br />
<br />
To update only the images named normal and fallback, run:<br />
<br />
flashrom -p prog -l rom.layout -i normal -i fallback -w some.rom<br />
<br />
Overlapping sections are not supported.</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x201&diff=14728Board:lenovo/x2012014-11-08T21:19:00Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X201 port.<br />
Issues:<br />
* Sometimes Gnome starts to think that battery is 10 time larger than real. Information from sysfs remains correct. Doesn't appear in newer gnome<br />
* Yellow USB port is not powered when computer is shut down or in S3.<br />
* No expresscard hotplug in windows (works fine if inserted on startup)<br />
<br />
<br />
Tested:<br />
* RAM module combinations of 4G+4G, 4G, 2G+2G,4G+2G, 2G<br />
* suspend to RAM (S3)<br />
* USB<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplug)<br />
* Sound<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload & SeaBIOS-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reeader.<br />
* Webcam<br />
* Bluetooth<br />
* Digitizer on X201t variant.<br />
Not tested:<br />
* Modem<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* [[Intel_Management_Engine|ME(Management Engine)] => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Code ==<br />
{{MergedIntoMaster|review_url=http://review.coreboot.org/#/c/4514/}}<br />
<br />
== Flashing ==<br />
Flash in X201 is divided roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* Rewriteable flash (3M-96K)<br />
* Locked bootblock (96K)<br />
<br />
Descriptor and bootblock are read-only. ME firmware is not readable.<br />
Rewriteable region can be rewritten easily with flashrom.<br />
<br />
For coreboot we need to preserve descriptor and ME firmware while overwriting<br />
rewriteable region and bootblock. To achieve this there are 2 ways:<br />
<br />
* External flasher.<br />
* Unlock bootblock<br />
<br />
For the first one proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the SPI chip which is under keyboard,<br />
around the position of trackpoint under protective layer. <br />
{|<br />
|[[File:Lenovo-x201-bios-location-arrow.png |200px|thumb|center|found it!]]<br />
|[[File:X201_flash_location.png |200px|thumb|center|under the keyboard]]<br />
|}<br />
[[File:Spi-soic8-25L6445E.png|200px|thumb|right|The flash chip]]<br />
<br />
I recommend using SOIC-8 clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
The pinout is as follows, the colors are buspirate colors<br />
=== front (display) ====<br />
3.3V (red) N/C violet (CLK) MOSI (gray)<br />
| | | |<br />
dot | | | |<br />
CS (white) MISO (black) N/C ground (brown)<br />
=== back (touchpad) ===<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x201/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x201/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot. Remember to enable HAVE_IFD and HAVE_ME_BIN<br />
* Flash the resulting build/coreboot.rom<br />
<br />
The other way has never been successfully used but it's known that the<br />
locking mechanism is in bootblock itself and that original firmware has<br />
a way to update it as follows:<br />
* Flash an update of rewriteable region. On next boot bootblock parses the<br />
image and sees that it contains a compressed copy of new bootblock. That<br />
copy is uncompressed and flashed.<br />
A way to unlock the bootblock would be to modify a firmware update to have a<br />
copy of bootblock without protection. For this you need to compress the<br />
modified block to fit into original space. The compression used is Lempel-Ziv-<br />
Huffman variant. I've written a compressor for it but unfortunately it's not<br />
performant enough.<br />
<br />
<br />
===identify the regions===<br />
[root@x201 ~]# flashrom -r bios.bin -pinternal:laptop=force_I_want_a_brick<br />
flashrom v0.9.6.1-r1563 on Linux 3.10-1-grml-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found chipset "Intel QM57". Enabling flash write... WARNING: SPI Configuration Lockdown activated.<br />
FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only.<br />
FREG2: WARNING: Management Engine region (0x00003000-0x004fffff) is locked.<br />
PR0: WARNING: 0x007d0000-0x01ffffff is read-only.<br />
Please send a verbose log to flashrom@flashrom.org if this board is not listed on<br />
http://flashrom.org/Supported_hardware#Supported_mainboards yet.<br />
Writes have been disabled. You can enforce write support with the<br />
ich_spi_force programmer option, but it will most likely harm your hardware!<br />
If you force flashrom you will get no support if something breaks.<br />
OK.<br />
Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000.<br />
Reading flash... FAILED.<br />
<br />
it will print the ME regions:<br />
FREG2: WARNING: Management Engine region (0x00003000-0x004fffff) is locked.<br />
it will also print the chip:<br />
Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000.<br />
'''But as in this case, flashrom might misidentify the chip''', this output is from [[Media:Spi-soic8-25L6445E.png|this MX25L6445E]]<br />
<br />
visually verify your chip's part number and find an [http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf appropriate datasheet ]<br />
<br />
=>verify that its voltage matches with the programmer voltage...<br />
* Then man flashrom says:<br />
-l, --layout <file><br />
Read ROM layout from <file>.<br />
<br />
flashrom supports ROM layouts. This allows you to flash<br />
certain parts of the flash chip only. A ROM layout file contains multiple lines<br />
with the following syntax:<br />
<br />
startaddr:endaddr imagename<br />
<br />
startaddr and endaddr are hexadecimal addresses within the ROM<br />
file and do not refer to any physical address. Please note that using a 0x<br />
prefix for those hexadecimal numbers is not necessary, but you can't<br />
specify decimal/octal numbers. imagename is an arbitrary name for the<br />
region/image from startaddr to endaddr (both addresses included).<br />
<br />
Example:<br />
<br />
00000000:00008fff gfxrom<br />
00009000:0003ffff normal<br />
00040000:0007ffff fallback<br />
<br />
If you only want to update the image named normal in a ROM based on the layout above, run<br />
<br />
flashrom -p prog --layout rom.layout --image normal -w some.rom<br />
<br />
To update only the images named normal and fallback, run:<br />
<br />
flashrom -p prog -l rom.layout -i normal -i fallback -w some.rom<br />
<br />
Overlapping sections are not supported.</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x220&diff=14726Board:lenovo/x2202014-11-06T21:36:44Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X220 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
* No expresscard hotplug in windows (works fine if inserted on startup, being worked on)<br />
<br />
Tested (and works):<br />
* RAM module combinations of 4G+0, 4G+4G<br />
* S3 (Suspend to RAM)<br />
* digitizer on x220t variant<br />
* WLAN (first minipcie slot)<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* Fn hotkeys<br />
* Video (both internal and VGA, including native gfx init)<br />
* touchpad<br />
* battery indicator<br />
* Fingerprint reader.<br />
* Thermal management<br />
* Webcam<br />
* Expresscard slot (including hotplugging)<br />
* USB (all 3 ports)<br />
* bluetooth<br />
* SD card slot<br />
* LAN<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* WWAN<br />
* WLAN slot USB<br />
* Windows (through SeaBIOS; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
<br />
Not tested:<br />
* Thinklight (probably works).<br />
* dock (probably works)<br />
* msata (probably works)<br />
* displayport (probably works)<br />
* USB 3.0 in some models (probably doesn't work)<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X220.jpg<br />
File:X220_chip.jpg<br />
File:X220_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed.<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x201&diff=14717Board:lenovo/x2012014-11-03T08:57:22Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X201 port.<br />
Issues:<br />
* Sometimes Gnome starts to think that battery is 10 time larger than real. Information from sysfs remains correct. Doesn't appear in newer gnome<br />
* Yellow USB port is not powered when computer is shut down or in S3.<br />
* No expresscard hotplug in windows (works fine if inserted on startup)<br />
<br />
<br />
Tested:<br />
* RAM module combinations of 4G+4G, 4G, 2G+2G,4G+2G, 2G<br />
* suspend to RAM (S3)<br />
* USB<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplug)<br />
* Sound<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload & SeaBIOS-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reeader.<br />
* Webcam<br />
* Bluetooth<br />
* Digitizer on X201t variant.<br />
Not tested:<br />
* Modem<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* [[Intel_Management_Engine|ME(Management Engine)] => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Code ==<br />
{{MergedIntoMaster|review_url=http://review.coreboot.org/#/c/4514/}}<br />
<br />
== Flashing ==<br />
Flash in X201 is divided roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* Rewriteable flash (3M-96K)<br />
* Locked bootblock (96K)<br />
<br />
Descriptor and bootblock are read-only. ME firmware is not readable.<br />
Rewriteable region can be rewritten easily with flashrom.<br />
<br />
For coreboot we need to preserve descriptor and ME firmware while overwriting<br />
rewriteable region and bootblock. To achieve this there are 2 ways:<br />
<br />
* External flasher.<br />
* Unlock bootblock<br />
<br />
For the first one proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the SPI chip which is under keyboard,<br />
around the position of trackpoint under protective layer. <br />
{|<br />
|[[File:Lenovo-x201-bios-location-arrow.png |200px|thumb|center|found it!]]<br />
|[[File:X201_flash_location.png |200px|thumb|center|under the keyboard]]<br />
|}<br />
[[File:Spi-soic8-25L6445E.png|200px|thumb|right|The flash chip]]<br />
<br />
I recommend using SOIC-8 clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
The pinout is as follows, the colors are buspirate colors<br />
=== front (display) ====<br />
3.3V (red) N/C violet (CLK) MOSI (gray)<br />
| | | |<br />
dot | | | |<br />
CS (white) MISO (black) N/C ground (brown)<br />
=== back (touchpad) ===<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x201/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x201/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
The other way has never been successfully used but it's known that the<br />
locking mechanism is in bootblock itself and that original firmware has<br />
a way to update it as follows:<br />
* Flash an update of rewriteable region. On next boot bootblock parses the<br />
image and sees that it contains a compressed copy of new bootblock. That<br />
copy is uncompressed and flashed.<br />
A way to unlock the bootblock would be to modify a firmware update to have a<br />
copy of bootblock without protection. For this you need to compress the<br />
modified block to fit into original space. The compression used is Lempel-Ziv-<br />
Huffman variant. I've written a compressor for it but unfortunately it's not<br />
performant enough.<br />
<br />
<br />
===identify the regions===<br />
[root@x201 ~]# flashrom -r bios.bin -pinternal:laptop=force_I_want_a_brick<br />
flashrom v0.9.6.1-r1563 on Linux 3.10-1-grml-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found chipset "Intel QM57". Enabling flash write... WARNING: SPI Configuration Lockdown activated.<br />
FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only.<br />
FREG2: WARNING: Management Engine region (0x00003000-0x004fffff) is locked.<br />
PR0: WARNING: 0x007d0000-0x01ffffff is read-only.<br />
Please send a verbose log to flashrom@flashrom.org if this board is not listed on<br />
http://flashrom.org/Supported_hardware#Supported_mainboards yet.<br />
Writes have been disabled. You can enforce write support with the<br />
ich_spi_force programmer option, but it will most likely harm your hardware!<br />
If you force flashrom you will get no support if something breaks.<br />
OK.<br />
Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000.<br />
Reading flash... FAILED.<br />
<br />
it will print the ME regions:<br />
FREG2: WARNING: Management Engine region (0x00003000-0x004fffff) is locked.<br />
it will also print the chip:<br />
Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000.<br />
'''But as in this case, flashrom might misidentify the chip''', this output is from [[Media:Spi-soic8-25L6445E.png|this MX25L6445E]]<br />
<br />
visually verify your chip's part number and find an [http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf appropriate datasheet ]<br />
<br />
=>verify that its voltage matches with the programmer voltage...<br />
* Then man flashrom says:<br />
-l, --layout <file><br />
Read ROM layout from <file>.<br />
<br />
flashrom supports ROM layouts. This allows you to flash<br />
certain parts of the flash chip only. A ROM layout file contains multiple lines<br />
with the following syntax:<br />
<br />
startaddr:endaddr imagename<br />
<br />
startaddr and endaddr are hexadecimal addresses within the ROM<br />
file and do not refer to any physical address. Please note that using a 0x<br />
prefix for those hexadecimal numbers is not necessary, but you can't<br />
specify decimal/octal numbers. imagename is an arbitrary name for the<br />
region/image from startaddr to endaddr (both addresses included).<br />
<br />
Example:<br />
<br />
00000000:00008fff gfxrom<br />
00009000:0003ffff normal<br />
00040000:0007ffff fallback<br />
<br />
If you only want to update the image named normal in a ROM based on the layout above, run<br />
<br />
flashrom -p prog --layout rom.layout --image normal -w some.rom<br />
<br />
To update only the images named normal and fallback, run:<br />
<br />
flashrom -p prog -l rom.layout -i normal -i fallback -w some.rom<br />
<br />
Overlapping sections are not supported.</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x230&diff=14716Board:lenovo/x2302014-11-03T08:57:00Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X230 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
<br />
Tested:<br />
* S3 (Suspend to RAM)<br />
* RAM module combinations of 8G+8G, 8G+0, 0+8G, 4G+8G, 8G+4G, 8G+1G, 1G+0, 0+1G, 4G+0, 0+4G<br />
* USB (both 2.0 and 3.0 ports)<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplugging)<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reader.<br />
* Webcam<br />
* trackpoint<br />
* touchpad<br />
* Fn hotkeys<br />
* Keyboard backlight<br />
* Thinklight.<br />
* bluetooth<br />
* dock<br />
* msata (fixed in commit c8f54a1109072706e2fa091dc9ab4ad3eb057b42)<br />
* mini displayport<br />
Not tested:<br />
* digitizer on x230t variant (may need work, if you have x230t and install coreboot on it please contact us)<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Code ==<br />
{{MergedIntoMaster}}<br />
<br />
== Flashing ==<br />
X230 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X230.jpg<br />
File:X230_chip.jpg<br />
File:X230_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. IF you've chosen CBFS_SIZE 4M or smaller that' the only chip you need to reflash.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed. If the file is 8M, you're flashing wrong chip, connec to the right one.<br />
<br />
* Write the flash. Since you have to write only top 4M, first split out those 4M:<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
* Use flashrom to flash top.rom.<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x220&diff=14715Board:lenovo/x2202014-11-03T08:56:31Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X220 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
* Fingerprint reader lenvo software doesn't find fingerprint reader in windows<br />
* No expresscard hotplug in windows (works fine if inserted on startup, being worked on)<br />
<br />
Tested (and works):<br />
* RAM module combinations of 4G+0, 4G+4G<br />
* S3 (Suspend to RAM)<br />
* digitizer on x220t variant<br />
* WLAN (first minipcie slot)<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* Fn hotkeys<br />
* Video (both internal and VGA, including native gfx init)<br />
* touchpad<br />
* battery indicator<br />
* Fingerprint reader.<br />
* Thermal management<br />
* Webcam<br />
* Expresscard slot (including hotplugging)<br />
* USB (all 3 ports)<br />
* bluetooth<br />
* SD card slot<br />
* LAN<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* WWAN<br />
* WLAN slot USB<br />
* Windows (through SeaBIOS; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
<br />
Not tested:<br />
* Thinklight (probably works).<br />
* dock (probably works)<br />
* msata (probably works)<br />
* displayport (probably works)<br />
* USB 3.0 in some models (probably doesn't work)<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X220.jpg<br />
File:X220_chip.jpg<br />
File:X220_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed.<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x220&diff=14709Board:lenovo/x2202014-10-26T21:55:48Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X220 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
* No wifi in windows (works fine if you replace the card with a non-intel model, being worked on)<br />
* No expresscard hotplug in windows (works fine if inserted on startup, being worked on)<br />
<br />
Tested (and works):<br />
* RAM module combinations of 4G+0, 4G+4G<br />
* S3 (Suspend to RAM)<br />
* digitizer on x220t variant<br />
* WLAN (first minipcie slot)<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* Fn hotkeys<br />
* Video (both internal and VGA, including native gfx init)<br />
* touchpad<br />
* battery indicator<br />
* Fingerprint reader.<br />
* Thermal management<br />
* Webcam<br />
* Expresscard slot (including hotplugging)<br />
* USB (all 3 ports)<br />
* bluetooth<br />
* SD card slot<br />
* LAN<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* WWAN<br />
* WLAN slot USB<br />
* Windows (through SeaBIOS; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
<br />
Not tested:<br />
* Thinklight (probably works).<br />
* dock (probably works)<br />
* msata (probably works)<br />
* displayport (probably works)<br />
* USB 3.0 in some models (probably doesn't work)<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X220.jpg<br />
File:X220_chip.jpg<br />
File:X220_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed.<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14134Board:lenovo/t5302014-09-15T15:05:54Z<p>Phcoder: Undo revision 14133 by Eocallaghan (talk)</p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Status ==<br />
Thanks for your interest in Lenovo T530 port.<br />
Issues:<br />
* EHCI output failure after sysagent<br />
* no S3<br />
* no MRC cache<br />
* MRC needs watchdog<br />
* yellow USB port isn't powered in power-off state.<br />
<br />
(Tested on X230 *not tested* on the T530):<br />
* RAM module combinations of 8G+8G<br />
* USB (both 2.0 and 3.0 ports)<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplugging)<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reader.<br />
* Webcam<br />
* Keyboard backlight<br />
* Thinklight.<br />
* bluetooth<br />
* dock<br />
* msata (fixed in commit c8f54a1109072706e2fa091dc9ab4ad3eb057b42)<br />
Not tested:<br />
* mini displayport (probably works)<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* ME(Management Engine) => you do not have to touch it (just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it (just leave it where it is)<br />
<br />
== GPIO layout ==<br />
<br />
This information should not be considered reliable in any way, shape or form<br />
<br />
* GPIO57 - OUT - controls..<br />
<br />
== General Purpose Events layout ==<br />
<br />
* GPE? - EC SCI<br />
* GPE? - EC SMI<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. IF you've chosen CBFS_SIZE 4M or smaller that's the only chip you need to reflash.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed. If the file is 8M, you're flashing wrong chip, connect to the right one.<br />
<br />
* Write the flash. Since you have to write only top 4M, first split out those 4M:<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
* Use flashrom to flash top.rom.<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14132Board:lenovo/t5302014-09-15T14:15:55Z<p>Phcoder: /* Proprietary components status */</p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Status ==<br />
Thanks for your interest in Lenovo T530 port.<br />
Issues:<br />
* EHCI output failure after sysagent<br />
* no S3<br />
* no MRC cache<br />
* MRC needs watchdog<br />
* yellow USB port isn't powered in power-off state.<br />
<br />
(Tested on X230 *not tested* on the T530):<br />
* RAM module combinations of 8G+8G<br />
* USB (both 2.0 and 3.0 ports)<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplugging)<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reader.<br />
* Webcam<br />
* Keyboard backlight<br />
* Thinklight.<br />
* bluetooth<br />
* dock<br />
* msata (fixed in commit c8f54a1109072706e2fa091dc9ab4ad3eb057b42)<br />
Not tested:<br />
* mini displayport (probably works)<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* ME(Management Engine) => you do not have to touch it (just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it (just leave it where it is)<br />
<br />
== GPIO layout ==<br />
<br />
This information should not be considered reliable in any way, shape or form<br />
<br />
* GPIO57 - OUT - controls..<br />
<br />
== General Purpose Events layout ==<br />
<br />
* GPE? - EC SCI<br />
* GPE? - EC SMI<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. IF you've chosen CBFS_SIZE 4M or smaller that's the only chip you need to reflash.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed. If the file is 8M, you're flashing wrong chip, connect to the right one.<br />
<br />
* Write the flash. Since you have to write only top 4M, first split out those 4M:<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
* Use flashrom to flash top.rom.<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Motherboard_Porting_Guide&diff=14107Motherboard Porting Guide2014-08-31T19:19:36Z<p>Phcoder: /* Adjusting contents of new board directory */</p>
<hr />
<div><br />
== Motherboard Porting Guide ==<br />
<br />
Please note that this is WIP work.<br />
<br />
== HOWTO to find a way ==<br />
<br />
* find a model and manufacturer of your mobo<br />
* download these tools:<br />
# git clone http://review.coreboot.org/p/coreboot<br />
# superiotool ( cd coreboot/util/superiotool ; make ; sudo make install )<br />
# inteltool ( cd coreboot/util/inteltool ; make ; sudo make install )<br />
# ectool ( cd coreboot/util/ectool ; make ; sudo make install )<br />
# dmidecode ( cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode co dmidecode )<br />
# msrtool ( cd coreboot/util/msrtool ; ./configure ; make ; sudo make install )<br />
# nvramtool ( cd coreboot/util/nvramtool ; make ; sudo make install )<br />
# flashrom ( svn co svn://coreboot.org/flashrom/trunk flashrom )<br />
* make and install them (make; sudo make install) - you need at least libpci/pciutils<br />
* check that your distro have this tools and install them:<br />
# lspci<br />
# dmesg<br />
# acpitool<br />
# lspnp<br />
# lsusb<br />
# acpidump<br />
* Do this commands (# remove for the easy copypasting):<br />
lspci -nnvvvxxxx > lspci.log<br />
lspnp -vv > lspnp.log<br />
lsusb -vvv > lsusb.log<br />
superiotool -deV > superiotool.log<br />
inteltool -a > inteltool.log<br />
ectool > ectool.log<br />
msrtool > msrtool.log<br />
dmidecode > dmidecode.log<br />
biosdecode > biosdecode.log<br />
nvramtool -x > nvramtool.log<br />
dmesg > dmesg.log<br />
flashrom -V -p internal:laptop=force_I_want_a_brick > flashrom_info.log<br />
flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > flashrom_read.log<br />
acpidump > acpidump.log<br />
for x in /sys/class/sound/card0/hw*; do cat "$x/init_pin_configs" > pin_"$(basename "$x")"; done<br />
for x in /proc/asound/card0/codec#*; do cat "$x" > "$(basename "$x")"; done<br />
* Save all logs in safe place, and also rom.bin file. <br />
* Find what chip does your mobo use. The name of the chip is present in flashrom_info.log but is not always exact as some chips have several packaging variants (e.g. SOIC-16, SOIC-8 and TSOP). Consult [[http://flashrom.org/Technology]] for more info on possible chip formats. If possible make a high-resolution (600dpi or higher) scan of motherboard. Make a scan, not a photo as cameras typically don't have enough resolution to identify individual chips.<br />
* try to find information - what EC (if on laptop) or Super I/O chip (if any) is used in your mobo (may be some info in Service Manuals or Disassembly guides)<br />
* try to find your Super I/O / EC chip datasheet<br />
For laptop, additionally:<br />
* if you see that ectool return some fake staff - like only 'FF' or '00' - so you have custom EC configuration, it's a hard work for support<br />
* if you see that ectool return looks like 'right' output - you have a big chances for support<br />
* you need to find from thease outputs Super I/O / EC chip name, or if not see this - disassembly your laptop<br />
<br />
=== Preparing recovery method ===<br />
<br />
Inevitably when you develop coreboot there will be unbootable builds and so you need a way to unbrick your machine after a failed image. There are several ways to do so. Main ones are:<br />
* In-system Programming. For more info consult [[http://flashrom.org/ISP]]<br />
* Hotswap. Consult [[http://flashrom.org/Technology]]<br />
In any case you have to locate the flash chip. Note the chipname from flashrom output. Teardown your system and find that chip. For how it usually looks like consult [[http://flashrom.org/Technology]]. If you have a scanner, do a high-resolution scan of your board, it may be useful later.<br />
<br />
=== Selecting Similar Board ===<br />
<br />
Most important criteria for finding similar board is chipset. Look at northbridge (device 0:0.0) and southbridge (LPC controller) in the lspci output. grep through coreboot tree to find how those chipsets are named, then grep for chipset name (case-insensitive) to find a board which uses it. If there are several of them, try to match (in order of decreasing importance) system type (desktop/laptop), SuperI/O and manufacturer.<br />
<br />
<br />
=== Adding a new board ===<br />
<br />
This is a two step process. If you mainboard already exists, skip to next section.<br />
<br />
==== Adding a new vendor to tree ====<br />
<br />
Create a directory in src/mainboard with the same name as vendor name. Add to src/mainboard/Kconfig<br />
new vendor entry, the rest of this example uses "foo" vendor.<br />
<br />
config VENDOR_FOO<br />
bool "Foo"<br />
<br />
Add also a include for new Kconfig file which holds the vendor motherboards in the vendor directory<br />
<br />
source "src/mainboard/foo/Kconfig"<br />
<br />
Create a src/mainboard/foo/Kconfig, copy from other vendor, and change the vendor name. Delete all mainboards. <br />
<br />
==== Adding a new motherboard to tree ====<br />
<br />
Asume that vendor name is foo and board type is bar. Add new configuration item in src/mainboard/foo/Kconfig<br />
<br />
config BOARD_FOO_BAR<br />
bool "BAR"<br />
<br />
Add include for board specific config:<br />
<br />
source "src/mainboard/foo/bar/Kconfig"<br />
<br />
==== Adjusting contents of new board directory ====<br />
<br />
Now copy your similar board and start adjusting. Your first stop is the Kconfig.<br />
<br />
* You need to change the condition in the first line to match your board:<br />
<br />
-if BOARD_VENDOR_BAR<br />
+if BOARD_VENDOR_BAZ<br />
<br />
* Change MAINBOARD_DIR and names<br />
* Change device options to match your config<br />
* Next stop go to mainboard.c and adjust GPIO config based on inteltool dump above.<br />
* Now you can flash the image and see what fails. <br />
* Later adjust hda_verb.h to get sound working properly (use initial pin dumps for reference)<br />
<br />
Look through the options and adjust <br />
<br />
Adjust Kconfig to fit the new vendor/model name and dont forget to change MAINBOARD_DIR and MAINBOARD_PART_NUMBER.</div>Phcoderhttps://www.coreboot.org/index.php?title=Motherboard_Porting_Guide&diff=14092Motherboard Porting Guide2014-08-30T00:03:26Z<p>Phcoder: /* HOWTO to find a way */</p>
<hr />
<div><br />
== Motherboard Porting Guide ==<br />
<br />
Please note that this is WIP work.<br />
<br />
== HOWTO to find a way ==<br />
<br />
* find a model and manufacturer of your mobo<br />
* download these tools:<br />
# git clone http://review.coreboot.org/p/coreboot<br />
# superiotool ( cd coreboot/util/superiotool ; make ; sudo make install )<br />
# inteltool ( cd coreboot/util/inteltool ; make ; sudo make install )<br />
# ectool ( cd coreboot/util/ectool ; make ; sudo make install )<br />
# dmidecode ( cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode co dmidecode )<br />
# msrtool ( cd coreboot/util/msrtool ; ./configure ; make ; sudo make install )<br />
# nvramtool ( cd coreboot/util/nvramtool ; make ; sudo make install )<br />
# flashrom ( svn co svn://coreboot.org/flashrom/trunk flashrom )<br />
* make and install them (make; sudo make install) - you need at least libpci/pciutils<br />
* check that your distro have this tools and install them:<br />
# lspci<br />
# dmesg<br />
# acpitool<br />
# lspnp<br />
# lsusb<br />
# acpidump<br />
* Do this commands (# remove for the easy copypasting):<br />
lspci -nnvvvxxxx > lspci.log<br />
lspnp -vv > lspnp.log<br />
lsusb -vvv > lsusb.log<br />
superiotool -deV > superiotool.log<br />
inteltool -a > inteltool.log<br />
ectool > ectool.log<br />
msrtool > msrtool.log<br />
dmidecode > dmidecode.log<br />
biosdecode > biosdecode.log<br />
nvramtool -x > nvramtool.log<br />
dmesg > dmesg.log<br />
flashrom -V -p internal:laptop=force_I_want_a_brick > flashrom_info.log<br />
flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > flashrom_read.log<br />
acpidump > acpidump.log<br />
for x in /sys/class/sound/card0/hw*; do cat "$x/init_pin_configs" > pin_"$(basename "$x")"; done<br />
for x in /proc/asound/card0/codec#*; do cat "$x" > "$(basename "$x")"; done<br />
* Save all logs in safe place, and also rom.bin file. <br />
* Find what chip does your mobo use. The name of the chip is present in flashrom_info.log but is not always exact as some chips have several packaging variants (e.g. SOIC-16, SOIC-8 and TSOP). Consult [[http://flashrom.org/Technology]] for more info on possible chip formats. If possible make a high-resolution (600dpi or higher) scan of motherboard. Make a scan, not a photo as cameras typically don't have enough resolution to identify individual chips.<br />
* try to find information - what EC (if on laptop) or Super I/O chip (if any) is used in your mobo (may be some info in Service Manuals or Disassembly guides)<br />
* try to find your Super I/O / EC chip datasheet<br />
For laptop, additionally:<br />
* if you see that ectool return some fake staff - like only 'FF' or '00' - so you have custom EC configuration, it's a hard work for support<br />
* if you see that ectool return looks like 'right' output - you have a big chances for support<br />
* you need to find from thease outputs Super I/O / EC chip name, or if not see this - disassembly your laptop<br />
<br />
=== Preparing recovery method ===<br />
<br />
Inevitably when you develop coreboot there will be unbootable builds and so you need a way to unbrick your machine after a failed image. There are several ways to do so. Main ones are:<br />
* In-system Programming. For more info consult [[http://flashrom.org/ISP]]<br />
* Hotswap. Consult [[http://flashrom.org/Technology]]<br />
In any case you have to locate the flash chip. Note the chipname from flashrom output. Teardown your system and find that chip. For how it usually looks like consult [[http://flashrom.org/Technology]]. If you have a scanner, do a high-resolution scan of your board, it may be useful later.<br />
<br />
=== Selecting Similar Board ===<br />
<br />
Most important criteria for finding similar board is chipset. Look at northbridge (device 0:0.0) and southbridge (LPC controller) in the lspci output. grep through coreboot tree to find how those chipsets are named, then grep for chipset name (case-insensitive) to find a board which uses it. If there are several of them, try to match (in order of decreasing importance) system type (desktop/laptop), SuperI/O and manufacturer.<br />
<br />
<br />
=== Adding a new board ===<br />
<br />
This is a two step process. If you mainboard already exists, skip to next section.<br />
<br />
==== Adding a new vendor to tree ====<br />
<br />
Create a directory in src/mainboard with the same name as vendor name. Add to src/mainboard/Kconfig<br />
new vendor entry, the rest of this example uses "foo" vendor.<br />
<br />
config VENDOR_FOO<br />
bool "Foo"<br />
<br />
Add also a include for new Kconfig file which holds the vendor motherboards in the vendor directory<br />
<br />
source "src/mainboard/foo/Kconfig"<br />
<br />
Create a src/mainboard/foo/Kconfig, copy from other vendor, and change the vendor name. Delete all mainboards. <br />
<br />
==== Adding a new motherboard to tree ====<br />
<br />
Asume that vendor name is foo and board type is bar. Add new configuration item in src/mainboard/foo/Kconfig<br />
<br />
config BOARD_FOO_BAR<br />
bool "BAR"<br />
<br />
Add include for board specific config:<br />
<br />
source "src/mainboard/foo/bar/Kconfig"<br />
<br />
==== Adjusting contents of new board directory ====<br />
<br />
Now copy your similar board and start adjusting. Your first stop is the Kconfig.<br />
<br />
* You need to change the condition in the first line to match your board:<br />
<br />
-if BOARD_VENDOR_BAR<br />
+if BOARD_VENDOR_BAZ<br />
<br />
* Change MAINBOARD_DIR and names<br />
* Change device options to match your config<br />
* Next stop go to mainboard.c and adjust GPIO config based on inteltool dump above.<br />
<br />
Look through the options and adjust <br />
<br />
Adjust Kconfig to fit the new vendor/model name and dont forget to change MAINBOARD_DIR and MAINBOARD_PART_NUMBER.</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x220&diff=14090Board:lenovo/x2202014-08-27T20:23:08Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X220 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
* No wifi in windows (works fine if you replace the card with a non-intel model, being worked on)<br />
* No speakers in windows (headset is fine, being worked on)<br />
* No expresscard hotplug in windows (works fine if inserted on startup, being worked on)<br />
<br />
Tested (and works):<br />
* RAM module combinations of 4G+0, 4G+4G<br />
* S3 (Suspend to RAM)<br />
* digitizer on x220t variant<br />
* WLAN (first minipcie slot)<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* Fn hotkeys<br />
* Video (both internal and VGA, including native gfx init)<br />
* touchpad<br />
* battery indicator<br />
* Fingerprint reader.<br />
* Thermal management<br />
* Webcam<br />
* Expresscard slot (including hotplugging)<br />
* USB (all 3 ports)<br />
* bluetooth<br />
* SD card slot<br />
* LAN<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* WWAN<br />
* WLAN slot USB<br />
* Windows (through SeaBIOS; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
<br />
Not tested:<br />
* Thinklight (probably works).<br />
* dock (probably works)<br />
* msata (probably works)<br />
* displayport (probably works)<br />
* USB 3.0 in some models (probably doesn't work)<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X220.jpg<br />
File:X220_chip.jpg<br />
File:X220_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed.<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x220&diff=14089Board:lenovo/x2202014-08-27T19:46:19Z<p>Phcoder: /* Status */</p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X220 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
* No wifi in windows (works fine if you replace the card with a non-intel model)<br />
* No speakers in windows (headset is fine)<br />
* No expresscard hotplug in windows (works fine if inserted on startup)<br />
<br />
Tested (and works):<br />
* RAM module combinations of 4G+0, 4G+4G<br />
* S3 (Suspend to RAM)<br />
* digitizer on x220t variant<br />
* WLAN (first minipcie slot)<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* Fn hotkeys<br />
* Video (both internal and VGA, including native gfx init)<br />
* touchpad<br />
* battery indicator<br />
* Fingerprint reader.<br />
* Thermal management<br />
* Webcam<br />
* Expresscard slot (including hotplugging)<br />
* USB (all 3 ports)<br />
* bluetooth<br />
* SD card slot<br />
* LAN<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* WWAN<br />
* WLAN slot USB<br />
* Windows (through SeaBIOS; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
<br />
Not tested:<br />
* Thinklight (probably works).<br />
* dock (probably works)<br />
* msata (probably works)<br />
* displayport (probably works)<br />
* USB 3.0 in some models (probably doesn't work)<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X220.jpg<br />
File:X220_chip.jpg<br />
File:X220_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed.<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x201&diff=14088Board:lenovo/x2012014-08-25T23:35:58Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X201 port.<br />
Issues:<br />
* Sometimes Gnome starts to think that battery is 10 time larger than real. Information from sysfs remains correct. Doesn't appear in newer gnome<br />
* Yellow USB port is not powered when computer is shut down or in S3.<br />
* No wifi in windows<br />
* No expresscard hotplug in windows (works fine if inserted on startup)<br />
<br />
<br />
Tested:<br />
* RAM module combinations of 4G+4G, 4G, 2G+2G,4G+2G, 2G<br />
* suspend to RAM (S3)<br />
* USB<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplug)<br />
* Sound<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reeader.<br />
* Webcam<br />
* Bluetooth<br />
* Digitizer on X201t variant.<br />
Not tested:<br />
* Modem<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Code ==<br />
* [http://review.coreboot.org/#/c/4514/ The code has been merged into coreboot master]<br />
<br />
$ git clone http://review.coreboot.org/p/coreboot<br />
<br />
== Flashing ==<br />
Flash in X201 is divided roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* Rewriteable flash (3M-96K)<br />
* Locked bootblock (96K)<br />
<br />
Descriptor and bootblock are read-only. ME firmware is not readable.<br />
Rewriteable region can be rewritten easily with flashrom.<br />
<br />
For coreboot we need to preserve descriptor and ME firmware while overwriting<br />
rewriteable region and bootblock. To achieve this there are 2 ways:<br />
<br />
* External flasher.<br />
* Unlock bootblock<br />
<br />
For the first one proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the SPI chip which is under keyboard,<br />
around the position of trackpoint under protective layer. <br />
{|<br />
|[[File:Lenovo-x201-bios-location-arrow.png |200px|thumb|center|found it!]]<br />
|[[File:X201_flash_location.png |200px|thumb|center|under the keyboard]]<br />
|}<br />
[[File:Spi-soic8-25L6445E.png|200px|thumb|right|The flash chip]]<br />
<br />
I recommend using SOIC-8 clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
The pinout is as follows, the colors are buspirate colors<br />
=== front (display) ====<br />
3.3V (red) N/C violet (CLK) MOSI (gray)<br />
| | | |<br />
dot | | | |<br />
CS (white) MISO (black) N/C ground (brown)<br />
=== back (touchpad) ===<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x201/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x201/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
The other way has never been successfully used but it's known that the<br />
locking mechanism is in bootblock itself and that original firmware has<br />
a way to update it as follows:<br />
* Flash an update of rewriteable region. On next boot bootblock parses the<br />
image and sees that it contains a compressed copy of new bootblock. That<br />
copy is uncompressed and flashed.<br />
A way to unlock the bootblock would be to modify a firmware update to have a<br />
copy of bootblock without protection. For this you need to compress the<br />
modified block to fit into original space. The compression used is Lempel-Ziv-<br />
Huffman variant. I've written a compressor for it but unfortunately it's not<br />
performant enough.<br />
<br />
<br />
===identify the regions===<br />
[root@x201 ~]# flashrom -r bios.bin -pinternal:laptop=force_I_want_a_brick<br />
flashrom v0.9.6.1-r1563 on Linux 3.10-1-grml-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found chipset "Intel QM57". Enabling flash write... WARNING: SPI Configuration Lockdown activated.<br />
FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only.<br />
FREG2: WARNING: Management Engine region (0x00003000-0x004fffff) is locked.<br />
PR0: WARNING: 0x007d0000-0x01ffffff is read-only.<br />
Please send a verbose log to flashrom@flashrom.org if this board is not listed on<br />
http://flashrom.org/Supported_hardware#Supported_mainboards yet.<br />
Writes have been disabled. You can enforce write support with the<br />
ich_spi_force programmer option, but it will most likely harm your hardware!<br />
If you force flashrom you will get no support if something breaks.<br />
OK.<br />
Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000.<br />
Reading flash... FAILED.<br />
<br />
it will print the ME regions:<br />
FREG2: WARNING: Management Engine region (0x00003000-0x004fffff) is locked.<br />
it will also print the chip:<br />
Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000.<br />
'''But as in this case, flashrom might misidentify the chip''', this output is from [[Media:Spi-soic8-25L6445E.png|this MX25L6445E]]<br />
<br />
visually verify your chip's part number and find an [http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf appropriate datasheet ]<br />
<br />
=>verify that its voltage matches with the programmer voltage...<br />
* Then man flashrom says:<br />
-l, --layout <file><br />
Read ROM layout from <file>.<br />
<br />
flashrom supports ROM layouts. This allows you to flash<br />
certain parts of the flash chip only. A ROM layout file contains multiple lines<br />
with the following syntax:<br />
<br />
startaddr:endaddr imagename<br />
<br />
startaddr and endaddr are hexadecimal addresses within the ROM<br />
file and do not refer to any physical address. Please note that using a 0x<br />
prefix for those hexadecimal numbers is not necessary, but you can't<br />
specify decimal/octal numbers. imagename is an arbitrary name for the<br />
region/image from startaddr to endaddr (both addresses included).<br />
<br />
Example:<br />
<br />
00000000:00008fff gfxrom<br />
00009000:0003ffff normal<br />
00040000:0007ffff fallback<br />
<br />
If you only want to update the image named normal in a ROM based on the layout above, run<br />
<br />
flashrom -p prog --layout rom.layout --image normal -w some.rom<br />
<br />
To update only the images named normal and fallback, run:<br />
<br />
flashrom -p prog -l rom.layout -i normal -i fallback -w some.rom<br />
<br />
Overlapping sections are not supported.</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x220&diff=14087Board:lenovo/x2202014-08-24T23:23:28Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X220 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
* No wifi in windows<br />
* No speakers in windows (headset is fine)<br />
* No expresscard hotplug in windows (works fine if inserted on startup)<br />
<br />
Tested (and works):<br />
* RAM module combinations of 4G+0, 4G+4G<br />
* S3 (Suspend to RAM)<br />
* digitizer on x220t variant<br />
* WLAN (first minipcie slot)<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* Fn hotkeys<br />
* Video (both internal and VGA, including native gfx init)<br />
* touchpad<br />
* battery indicator<br />
* Fingerprint reader.<br />
* Thermal management<br />
* Webcam<br />
* Expresscard slot (including hotplugging)<br />
* USB (all 3 ports)<br />
* bluetooth<br />
* SD card slot<br />
* LAN<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* WWAN<br />
* WLAN slot USB<br />
* Windows (through SeaBIOS; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
<br />
Not tested:<br />
* Thinklight (probably works).<br />
* dock (probably works)<br />
* msata (probably works)<br />
* displayport (probably works)<br />
* USB 3.0 in some models (probably doesn't work)<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X220.jpg<br />
File:X220_chip.jpg<br />
File:X220_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed.<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:apple/macbook21&diff=14086Board:apple/macbook212014-08-24T20:59:40Z<p>Phcoder: </p>
<hr />
<div>Tested on a MacBook2,1 (Mid 2007) 2.0 GHz Core 2 Duo, Model No: A1181 (EMC 2139) with GRUB2 payload.<br />
<br />
The tested machine is as described here: [http://www.everymac.com/systems/apple/macbook/specs/macbook-core-2-duo-2.0-white-13-mid-2007-specs.html] with the one difference that the vendor's EFI architecture in fact is 32-Bit.<br />
<br />
The port might work as well, but is not yet tested on MacBook2,1 (Late 2006) and MacBook1,1. The latter might require small code modifications, e.g. for DMI machine identification.<br />
<br />
UPDATE:<br />
MacBook1,1 does work, but required external flashing for initial install. (see notes on libreboot.org/docs or dev.libreboot.org/docs)<br />
(also, see notes about cpu temperatures / fan speeds)<br />
<br />
==Hardware==<br />
==Status==<br />
Payload:<br />
* GRUB2 works<br />
* no other payload tested yet<br />
<br />
Operating System:<br />
* GNU/Linux-libre works<br />
* GNU/Linux works<br />
* Windows works (tested with Windows 8.1 x86 [x86 because mine has only 1GiB of RAM])<br />
* FreeBSD works (not a lot of tests were done though)<br />
* OS X is untested<br />
<br />
Issues under GNU/Linux-libre and GNU/Linux:<br />
* The machine's one and only led lights up during boot which is fine. At some point during or after boot it should turn off though. At the moment it just stays turned on for ever. During suspend to RAM, the led blinks which is just nice. After resume from suspend to RAM the led turn off. This is what should happen after a normal boot too.<br />
* "00:07.0 Performance counters [1101]: Intel Corporation Device [8086:27a3] (rev 03)" is hidden under coreboot. What's its function anyway?<br />
* No CPU temperature indicator<br />
* Idle power consumption is higher than with vendor firmware (no C-states)<br />
* Suspend to disk aka hibernate works. Although:<br />
** While it goes into hibernate state the screen turns off but then turns on again for just about a few seconds before it finaly turns off.<br />
** When resuming/powering on, the keyboard is dead in the payload/GRUB2. Since '''my''' GRUB2 image is configured to boot a default menu entry after a few seconds of no user input, it then starts GNU/Linux-libre nicely. That is, the keyboard works to enter for example the LUKS passphrase which then unlocks the swap partition and the machine's state from before hibernate gets restored.<br />
** Since I never used hibernate before, I can not say if the described behaviour is just normal or an issue.<br />
<br />
Issues under Windows:<br />
* no hotkeys<br />
* no sound (Apple driver fails to install)<br />
* backlight occasionally drops to 0 after suspend<br />
* no backlight control<br />
* CD untested<br />
* no webcam (not even with Apple drivers)<br />
* bluetooth untested<br />
* no restart<br />
<br />
Apple-specific drivers needed in Windows:<br />
* Webcam<br />
* Touchpad (to get right click)<br />
* Keyboard (for some Fn combinations)<br />
* Sound<br />
<br />
Tested and works on both GNU/Linux and Windows unless otherwise specified in previous section:<br />
* RAM 3 GB (1x2 GB + 1x1 GB), 1GB (2 x 512M)<br />
* Keyboard<br />
* Touchpad<br />
* Screen<br />
* Ethernet<br />
* Wifi<br />
* Sound (internal speakers, headphones, microphone, external microphone)<br />
* External USB connectors<br />
* Fan<br />
* Suspend to RAM<br />
* Decrease and increase the screen backlight works<br />
* Optical drive<br />
* Webcam (needs non-free driver, so it does not work with Linux-libre)<br />
* Internal HDD<br />
* Bluetooth<br />
* wake on LID in S3<br />
<br />
Not tested:<br />
* External Firewire connector<br />
* External monitor connector<br />
* Infrared receiver<br />
<br />
==Proprietary components==<br />
<br />
==Code==<br />
Not yet merged into master. It's under review and will be improved. See<br />
* [http://review.coreboot.org/#/c/5321/ http://review.coreboot.org/#/c/5321/]<br />
* [http://review.coreboot.org/#/c/5323/ http://review.coreboot.org/#/c/5323/]<br />
* [http://review.coreboot.org/#/c/5324/ http://review.coreboot.org/#/c/5324/]<br />
==Configure coreboot==<br />
When starting without any <code>.config</code> file you might want to configure coreboot by<br />
<pre><br />
make menuconfig<br />
</pre><br />
At a minimum make the following selections:<br />
<pre><br />
Mainboard ---><br />
Mainboard vendor ---><br />
Apple<br />
Mainboard model ---><br />
MacBook1,1 or MacBook2,1 (choose the right one)<br />
Devices ---><br />
[*] Use native graphics initialization<br />
Payload ---><br />
Add a payload ---><br />
An ELF executable payload<br />
Payload path and filename # Insert the path and filename to<br />
# the standalone GRUB2 image to be used<br />
</pre><br />
Moreover, you might want to disable the usage of CPU microcode:<br />
<pre><br />
Chipset ---><br />
*** CPU ***<br />
Include CPU microcode in CBFS ---> <br />
Do not include microcode updates<br />
</pre><br />
<br />
==Flashing==<br />
Flashing is easy with the vendor BIOS version [http://support.apple.com/downloads/MacBook_EFI_Firmware_Update_1_1 MB21.00A5.B07 (EFI 1.1)] installed. Maybe see also this page for a more recent verion: [http://support.apple.com/kb/HT1237 EFI and SMC firmware updates for Intel-based Macs].<br />
<br />
===Identify the flash chip===<br />
Make sure flashrom can identify the flash chip:<br />
<pre><br />
# flashrom --verbose --programmer internal:laptop=force_I_want_a_brick >flashrom_info.log<br />
</pre><br />
The output should involve:<br />
<pre><br />
...<br />
DMI string system-manufacturer: "Apple Inc."<br />
DMI string system-product-name: "MacBook2,1"<br />
DMI string system-version: "1.0"<br />
DMI string baseboard-manufacturer: "Apple Inc."<br />
DMI string baseboard-product-name: "Mac-F4208CAA"<br />
DMI string baseboard-version: "PVT"<br />
DMI string chassis-type: "Notebook"<br />
Laptop detected via DMI.<br />
Found chipset "Intel ICH7M" with PCI ID 8086:27b9. Enabling flash write... <br />
...<br />
Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541<br />
Found SST flash chip "SST25VF016B" (2048 kB, SPI) at physical address 0xffe00000.<br />
Chip status register is 0x1c.<br />
Chip status register: Block Protect Write Disable (BPL) is not set<br />
Chip status register: Auto Address Increment Programming (AAI) is not set<br />
Chip status register: Block Protect 3 (BP3) is not set<br />
Chip status register: Block Protect 2 (BP2) is set<br />
Chip status register: Block Protect 1 (BP1) is set<br />
Chip status register: Block Protect 0 (BP0) is set<br />
Chip status register: Write Enable Latch (WEL) is not set<br />
Chip status register: Write In Progress (WIP/BUSY) is not set<br />
Resulting block protection : all<br />
...<br />
Found SST flash chip "SST25VF016B" (2048 kB, SPI).<br />
No operations were specified.<br />
...<br />
</pre><br />
<br />
'''If it does not find this very same chip but rather finds a different chip or none at all: stop here and think twice.'''<br />
<br />
===Read the vendor BIOS===<br />
Read the vendor BIOS and store it in a safe place (possibly at two different places outside the MacBook).<br />
<pre><br />
# flashrom --verbose --programmer internal:laptop=force_I_want_a_brick --chip SST25VF016B \<br />
--read rom.bin >flashrom_read.log 2>&1<br />
</pre><br />
The output should involve:<br />
<pre><br />
...<br />
Found SST flash chip "SST25VF016B" (2048 kB, SPI) at physical address 0xffe00000.<br />
...<br />
Resulting block protection : none<br />
Reading flash... done.<br />
...<br />
</pre><br />
<br />
===Write coreboot===<br />
Note, the following won't work on the Macbook1,1 (external flashing required). [https://www.ifixit.com/Device/MacBook_Core_2_Duo disassembly guides here]<br />
<pre><br />
# flashrom --verbose --programmer internal:laptop=force_I_want_a_brick --chip SST25VF016B \<br />
--write coreboot.rom >flashrom_write.log 2>&1<br />
</pre><br />
The output should involve:<br />
<pre><br />
...<br />
Found SST flash chip "SST25VF016B" (2048 kB, SPI) at physical address 0xffe00000.<br />
...<br />
Resulting block protection : none<br />
coreboot last image size (not ROM size) is 2097152 bytes.<br />
Manufacturer: Apple<br />
Mainboard ID: MacBook2,1<br />
Reading old flash chip contents... done.<br />
Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:ETransaction error!<br />
Running OPCODE 0x20 failed at address 0x000000 (payload length was 0).<br />
spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Trying erase function 1... 0x000000-0x007fff:ETransaction error!<br />
Running OPCODE 0x52 failed at address 0x000000 (payload length was 0).<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Trying erase function 2... 0x000000-0x00ffff:ETransaction error!<br />
Running OPCODE 0xd8 failed at address 0x000000 (payload length was 0).<br />
spi_block_erase_d8 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Trying erase function 3... 0x000000-0x1fffff:EW<br />
Erase/write done.<br />
Verifying flash... VERIFIED.<br />
...<br />
</pre><br />
<br />
===Update coreboot===<br />
Once coreboot is installed, flashing an update coreboot version or reverting back to the vendor BIOS works with and without the <code>laptop=force_I_want_a_brick</code> switch.<br />
===Add it to flashrom's whitelist===<br />
MacBook2,1 can be added to flashrom's whitelist with this patch: [http://paste.flashrom.org/view.php?id=2047], so that the <code>laptop=force_I_want_a_brick</code> switch is no longer required when running the machine under the vendor's BIOS.</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x230&diff=14085Board:lenovo/x2302014-08-24T20:42:09Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X230 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
* No wifi in windows<br />
<br />
Tested:<br />
* S3 (Suspend to RAM)<br />
* RAM module combinations of 8G+8G, 8G+0, 0+8G, 4G+8G, 8G+4G, 8G+1G, 1G+0, 0+1G, 4G+0, 0+4G<br />
* USB (both 2.0 and 3.0 ports)<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplugging)<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reader.<br />
* Webcam<br />
* trackpoint<br />
* touchpad<br />
* Fn hotkeys<br />
* Keyboard backlight<br />
* Thinklight.<br />
* bluetooth<br />
* dock<br />
* msata (fixed in commit c8f54a1109072706e2fa091dc9ab4ad3eb057b42)<br />
* mini displayport<br />
Not tested:<br />
* digitizer on x230t variant (may need work, if you have x230t and install coreboot on it please contact us)<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Code ==<br />
* The code has been merged into coreboot master<br />
<br />
$ git clone http://review.coreboot.org/p/coreboot<br />
<br />
== Flashing ==<br />
X230 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X230.jpg<br />
File:X230_chip.jpg<br />
File:X230_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. IF you've chosen CBFS_SIZE 4M or smaller that' the only chip you need to reflash.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed. If the file is 8M, you're flashing wrong chip, connec to the right one.<br />
<br />
* Write the flash. Since you have to write only top 4M, first split out those 4M:<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
* Use flashrom to flash top.rom.<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x230&diff=14084Board:lenovo/x2302014-08-24T20:31:27Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X230 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
* No wifi in windows<br />
<br />
Tested:<br />
* S3 (Suspend to RAM)<br />
* RAM module combinations of 8G+8G, 8G+0, 0+8G, 4G+8G, 8G+4G, 8G+1G, 1G+0, 0+1G, 4G+0, 0+4G<br />
* USB (both 2.0 and 3.0 ports)<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplugging)<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reader.<br />
* Webcam<br />
* trackpoint<br />
* touchpad<br />
* Fn hotkeys<br />
* Keyboard backlight<br />
* Thinklight.<br />
* bluetooth<br />
* dock<br />
* msata (fixed in commit c8f54a1109072706e2fa091dc9ab4ad3eb057b42)<br />
Not tested:<br />
* mini displayport (probably works)<br />
* digitizer on x230t variant (may need work, if you have x230t and install coreboot on it please contact us)<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Code ==<br />
* The code has been merged into coreboot master<br />
<br />
$ git clone http://review.coreboot.org/p/coreboot<br />
<br />
== Flashing ==<br />
X230 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X230.jpg<br />
File:X230_chip.jpg<br />
File:X230_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. IF you've chosen CBFS_SIZE 4M or smaller that' the only chip you need to reflash.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed. If the file is 8M, you're flashing wrong chip, connec to the right one.<br />
<br />
* Write the flash. Since you have to write only top 4M, first split out those 4M:<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
* Use flashrom to flash top.rom.<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x220&diff=14082Board:lenovo/x2202014-08-24T15:38:51Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X220 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
* No wifi in windows<br />
* No speakers in windows (headset is fine)<br />
* No expresscard hotplug in windows (works fine if inserted on startup)<br />
<br />
Tested (and works):<br />
* RAM module combinations of 4G+0, 4G+4G<br />
* S3 (Suspend to RAM)<br />
* digitizer on x220t variant<br />
* WLAN (first minipcie slot)<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* Fn hotkeys<br />
* Video (both internal and VGA, including native gfx init)<br />
* touchpad<br />
* battery indicator<br />
* Fingerprint reader.<br />
* Thermal management<br />
* Webcam<br />
* Expresscard slot (including hotplugging)<br />
* USB (all 3 ports)<br />
* bluetooth<br />
* SD card slot<br />
* LAN<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* WWAN<br />
* WLAN slot USB<br />
* Windows (through SeaBIOS; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
<br />
Not tested:<br />
* Thinklight.<br />
* dock<br />
* msata<br />
* displayport (probably works)<br />
<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X220.jpg<br />
File:X220_chip.jpg<br />
File:X220_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed.<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x220&diff=14081Board:lenovo/x2202014-08-24T15:18:10Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X220 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
* No wifi in windows<br />
* No speakers in windows (headset is fine)<br />
* No expresscard in windows<br />
<br />
Tested (and works):<br />
* RAM module combinations of 4G+0, 4G+4G<br />
* S3 (Suspend to RAM)<br />
* digitizer on x220t variant<br />
* WLAN (first minipcie slot)<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* Fn hotkeys<br />
* Video (both internal and VGA, including native gfx init)<br />
* touchpad<br />
* battery indicator<br />
* Fingerprint reader.<br />
* Thermal management<br />
* Webcam<br />
* Expresscard slot (including hotplugging)<br />
* USB (all 3 ports)<br />
* bluetooth<br />
* SD card slot<br />
* LAN<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* WWAN<br />
* WLAN slot USB<br />
* Windows (through SeaBIOS; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
<br />
Not tested:<br />
* Thinklight.<br />
* dock<br />
* msata<br />
* displayport (probably works)<br />
<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X220.jpg<br />
File:X220_chip.jpg<br />
File:X220_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed.<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x220&diff=14080Board:lenovo/x2202014-08-24T15:17:42Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X220 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
* No wifi in windows<br />
* No speakers in windows (headset is fine)<br />
<br />
Tested (and works):<br />
* RAM module combinations of 4G+0, 4G+4G<br />
* S3 (Suspend to RAM)<br />
* digitizer on x220t variant<br />
* WLAN (first minipcie slot)<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* Fn hotkeys<br />
* Video (both internal and VGA, including native gfx init)<br />
* touchpad<br />
* battery indicator<br />
* Fingerprint reader.<br />
* Thermal management<br />
* Webcam<br />
* Expresscard slot (including hotplugging)<br />
* USB (all 3 ports)<br />
* bluetooth<br />
* SD card slot<br />
* LAN<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* WWAN<br />
* WLAN slot USB<br />
* Windows (through SeaBIOS; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
<br />
Not tested:<br />
* Thinklight.<br />
* dock<br />
* msata<br />
* displayport (probably works)<br />
<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X220.jpg<br />
File:X220_chip.jpg<br />
File:X220_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed.<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x220&diff=14079Board:lenovo/x2202014-08-24T12:54:50Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X220 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
* No wifi in windows<br />
* No sound in windows<br />
<br />
Tested (and works):<br />
* RAM module combinations of 4G+0, 4G+4G<br />
* S3 (Suspend to RAM)<br />
* digitizer on x220t variant<br />
* WLAN (first minipcie slot)<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* Fn hotkeys<br />
* Video (both internal and VGA, including native gfx init)<br />
* touchpad<br />
* battery indicator<br />
* Fingerprint reader.<br />
* Thermal management<br />
* Webcam<br />
* Expresscard slot (including hotplugging)<br />
* USB (all 3 ports)<br />
* bluetooth<br />
* SD card slot<br />
* LAN<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* WWAN<br />
* WLAN slot USB<br />
* Windows (through SeaBIOS; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
<br />
Not tested:<br />
* Thinklight.<br />
* dock<br />
* msata<br />
* displayport (probably works)<br />
<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X220.jpg<br />
File:X220_chip.jpg<br />
File:X220_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed.<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x220&diff=14078Board:lenovo/x2202014-08-24T12:36:13Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X220 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
* No wifi on windows<br />
<br />
Tested (and works):<br />
* RAM module combinations of 4G+0, 4G+4G<br />
* S3 (Suspend to RAM)<br />
* digitizer on x220t variant<br />
* WLAN (first minipcie slot)<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* Fn hotkeys<br />
* Video (both internal and VGA, including native gfx init)<br />
* touchpad<br />
* battery indicator<br />
* Fingerprint reader.<br />
* Thermal management<br />
* Webcam<br />
* Expresscard slot (including hotplugging)<br />
* USB (all 3 ports)<br />
* bluetooth<br />
* SD card slot<br />
* LAN<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* WWAN<br />
* WLAN slot USB<br />
* Windows (through SeaBIOS; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
<br />
Not tested:<br />
* Thinklight.<br />
* dock<br />
* msata<br />
* displayport (probably works)<br />
<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X220.jpg<br />
File:X220_chip.jpg<br />
File:X220_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed.<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x220&diff=14077Board:lenovo/x2202014-08-24T11:49:18Z<p>Phcoder: </p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X220 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
<br />
Tested (and works):<br />
* RAM module combinations of 4G+0, 4G+4G<br />
* S3 (Suspend to RAM)<br />
* digitizer on x220t variant<br />
* WLAN (first minipcie slot)<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* Fn hotkeys<br />
* Video (both internal and VGA, including native gfx init)<br />
* touchpad<br />
* battery indicator<br />
* Fingerprint reader.<br />
* Thermal management<br />
* Webcam<br />
* Expresscard slot (including hotplugging)<br />
* USB (all 3 ports)<br />
* bluetooth<br />
* SD card slot<br />
* LAN<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* WWAN<br />
* WLAN slot USB<br />
<br />
Not tested:<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* Thinklight.<br />
* dock<br />
* msata<br />
* displayport (probably works)<br />
<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X220.jpg<br />
File:X220_chip.jpg<br />
File:X220_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed.<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoderhttps://www.coreboot.org/index.php?title=Board:lenovo/x220&diff=14076Board:lenovo/x2202014-08-24T11:34:10Z<p>Phcoder: Created page with "== Status == Thanks for your interest in Lenovo X220 port. Issues: * no MRC cache (longer boot time) * yellow USB port isn't powered in power-off state. * Badly seated RAM may..."</p>
<hr />
<div>== Status ==<br />
Thanks for your interest in Lenovo X220 port.<br />
Issues:<br />
* no MRC cache (longer boot time)<br />
* yellow USB port isn't powered in power-off state.<br />
* Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)<br />
<br />
Tested (and works):<br />
* S3 (Suspend to RAM)<br />
* digitizer on x220t variant<br />
* WLAN (first minipcie slot)<br />
* Linux (through GRUB-as-payload)<br />
* trackpoint<br />
* Fn hotkeys<br />
* Video (both internal and VGA)<br />
* touchpad<br />
* battery indicator<br />
* Fingerprint reader.<br />
* Thermal management<br />
* Webcam<br />
* Expresscard slot (including hotplugging)<br />
* USB (all 3 ports)<br />
* bluetooth<br />
* SD card slot<br />
* LAN<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
<br />
Not tested:<br />
* WWAN<br />
* WLAN slot USB<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* Thinklight.<br />
* dock<br />
* msata<br />
* RAM module combinations of 8G+8G, 8G+0, 0+8G, 4G+8G, 8G+4G, 8G+1G, 1G+0, 0+1G, 4G+0, 0+4G<br />
* displayport (probably works)<br />
<br />
<br />
== proprietary components status ==<br />
* CPU Microcode<br />
* VGA option rom (optional): you need it if you wantgraphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Flashing ==<br />
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
<gallery><br />
File:X220.jpg<br />
File:X220_chip.jpg<br />
File:X220_clip.jpg<br />
</gallery><br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed.<br />
<br />
* Recover descriptor and me firmare:<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/descriptor.bin \<br />
count=12288 bs=1M iflag=count_bytes<br />
dd if=flash.bin of=coreboot/3rdparty/mainboard/lenovo/x220/me.bin \<br />
skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes<br />
* Compile coreboot<br />
* Flash the resulting build/coreboot.rom<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>Phcoder