https://www.coreboot.org/api.php?action=feedcontributions&user=Quux&feedformat=atomcoreboot - User contributions [en]2024-03-19T08:42:01ZUser contributionsMediaWiki 1.40.0https://www.coreboot.org/index.php?title=Build_HOWTO&diff=10209Build HOWTO2010-12-05T20:54:14Z<p>Quux: /* Building coreboot */ bin to upload</p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard using the '''kconfig''' system (a.k.a. '''make menuconfig''').<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++<br />
* make<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot subversion version:<br />
<br />
$ '''svn co svn://coreboot.org/coreboot/trunk coreboot'''<br />
$ '''cd coreboot'''<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on.<br />
* Enter the '''Payload''' menu.<br />
** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip. A ready-made binary A8NE.ROM tested and ready to 'flashrom' into your standard 512MB eeprom will be made available anytime soon now. Just download the binary, flash it & enjoy!<br />
<br />
== Flashing coreboot ==<br />
<br />
You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.<br />
<br />
== Manipulating coreboot images with cbfstool ==<br />
<br />
TODO</div>Quuxhttps://www.coreboot.org/index.php?title=Board:gigabyte/m57sli&diff=10203Board:gigabyte/m57sli2010-12-02T08:11:05Z<p>Quux: /* Which board do you have? */</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:gigabyte/m57sli&diff=10202Board:gigabyte/m57sli2010-12-02T08:02:40Z<p>Quux: /* Which board do you have? */ 4 versions</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:gigabyte/m57sli&diff=10201Board:gigabyte/m57sli2010-12-02T07:58:18Z<p>Quux: /* Which board do you have? */ 4 versions BIOS</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Developer_Manual/Tools&diff=10200Developer Manual/Tools2010-12-02T07:15:20Z<p>Quux: /* External EPROM/Flash programmer that can program the flash chip on your motherboard */</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Developer_Manual/Tools&diff=10199Developer Manual/Tools2010-12-02T07:14:54Z<p>Quux: /* External EPROM/Flash programmer that can program the flash chip on your motherboard */ RTL8139 32 pin plus ZIF socket adapter</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Talk:GIGABYTE_GA-M57SLI-S4&diff=10198Talk:GIGABYTE GA-M57SLI-S42010-12-02T07:03:19Z<p>Quux: legacy BIOS</p>
<hr />
<div>swap #CE and #WP and thus route #CE through the #WP jumper with 8 pin SPI possible ?<br />
--[[User:Quux|da Great QUUX]] 14:24, 28 April 2007 (CEST)<br />
<br />
<br />
----<br />
Alternatively, you might flip a standard plcc-32 socket over the mainboard-chip. then wire a secondary plcc-32 socket to it wired 1:1 - except you connect /reset and /oe on the replacment chip, while you route the /oe from the mainboard to an NC pin on the secondary chip. Take off (hot unplug) the socket after successful boot-up to reflash the original chip. (so called "top hat flash" method, use at own risk, no successful report on GA M57 yet)<br />
<br />
on GA M57SLI, is FWH mode used ? is it necessary to use different ID on ID-pins ?<br />
<br />
----<br />
'''badly in need:''' <br />
<br />
<br />
* is it practical to upgrade the secondary pad with an 2 MBit flash part ?<br />
<br />
''2 MByte:'' the southbridge needs to decode the full 2Mbyte (these are 16Mbit parts) address range for it to be useful in practice. A lot of the SB parts I looked at, years ago, reserved the top 2M of the 2 GB space. so it is something we have to check.<br />
----<br />
<br />
[http://sites.google.com/site/pinczakko/pinczakko-s-guide-to-ami-bios-reverse-engineering-1 Salihun] on '''AWARD''' ('legacy') BIOS re-engineering. AWARD is inside many boards by Gigabyte like M57SLI.</div>Quuxhttps://www.coreboot.org/index.php?title=Board:gigabyte/m57sli&diff=10197Board:gigabyte/m57sli2010-12-02T06:57:57Z<p>Quux: /* SOIC hardware hack */ Stuge's video talk (FOSSDEM)</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Talk:Gigabyte_m57sli_Vendor_Cooperation_Score&diff=10196Talk:Gigabyte m57sli Vendor Cooperation Score2010-12-02T06:49:11Z<p>Quux: award hacks</p>
<hr />
<div>remember, AWARD BIOS is quite hackable, still: [[http://sites.google.com/site/pinczakko/pinczakko-s-guide-to-ami-bios-reverse-engineering-1 Salihun]]</div>Quuxhttps://www.coreboot.org/index.php?title=Board:gigabyte/m57sli&diff=10195Board:gigabyte/m57sli2010-12-02T06:40:37Z<p>Quux: /* Which board do you have? */ latest BIOS rev.</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Developer_Manual/Tools&diff=10194Developer Manual/Tools2010-12-02T06:35:38Z<p>Quux: /* Top Hat Flash */ too bad it is not more common yet</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Talk:GIGABYTE_GA-M57SLI-S4&diff=10193Talk:GIGABYTE GA-M57SLI-S42010-12-02T06:26:16Z<p>Quux: BIOS reengineer</p>
<hr />
<div>swap #CE and #WP and thus route #CE through the #WP jumper with 8 pin SPI possible ?<br />
--[[User:Quux|da Great QUUX]] 14:24, 28 April 2007 (CEST)<br />
<br />
<br />
----<br />
Alternatively, you might flip a standard plcc-32 socket over the mainboard-chip. then wire a secondary plcc-32 socket to it wired 1:1 - except you connect /reset and /oe on the replacment chip, while you route the /oe from the mainboard to an NC pin on the secondary chip. Take off (hot unplug) the socket after successful boot-up to reflash the original chip. (so called "top hat flash" method, use at own risk, no successful report on GA M57 yet)<br />
<br />
on GA M57SLI, is FWH mode used ? is it necessary to use different ID on ID-pins ?<br />
<br />
----<br />
'''badly in need:''' <br />
<br />
<br />
* is it practical to upgrade the secondary pad with an 2 MBit flash part ?<br />
<br />
''2 MByte:'' the southbridge needs to decode the full 2Mbyte (these are 16Mbit parts) address range for it to be useful in practice. A lot of the SB parts I looked at, years ago, reserved the top 2M of the 2 GB space. so it is something we have to check.<br />
----<br />
<br />
[http://sites.google.com/site/pinczakko/pinczakko-s-guide-to-ami-bios-reverse-engineering-1 Salihun] on '''AWARD''' BIOS re-engineering. AWARD is inside many boards by Gigabyte like M57SLI.</div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=5499Board:asus/a8n e2007-12-19T03:45:26Z<p>Quux: /* Before you begin */ abuild issue</p>
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<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:gigabyte/m57sli&diff=5498Board:gigabyte/m57sli2007-12-19T00:23:10Z<p>Quux: /* Before you begin */</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=5497Board:asus/a8n e2007-12-19T00:20:46Z<p>Quux: /* Known issues */</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=5496Board:asus/a8n e2007-12-19T00:17:25Z<p>Quux: /* Before you begin */ svn co svn://linuxbios.org/buildrom then type "make menuconfig" but the A8NE is not supported there yet.</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=5495Board:asus/a8n e2007-12-18T23:13:58Z<p>Quux: /* Before you begin */</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=5491Board:asus/a8n e2007-12-18T08:23:40Z<p>Quux: /* Before you begin */ binary img</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=5488Board:asus/a8n e2007-12-18T07:29:01Z<p>Quux: /* Known issues */ populate 1 ram socket only</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=5487Board:asus/a8n e2007-12-18T07:27:25Z<p>Quux: /* Before you begin */ 508 kb only : fallback rom section size bug</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=5486Board:asus/a8n e2007-12-18T06:38:14Z<p>Quux: /* Before you begin */ no visible POST codes</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=5465Board:asus/a8n e2007-12-07T16:15:39Z<p>Quux: /* Before you begin */ "pre-programmed" might sound misleading as a prerequisite</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=FAQ&diff=5464FAQ2007-12-07T16:07:01Z<p>Quux: /* External EPROM/Flash programmer that can program the flash on your motherboard */ external may not be necessary for starters</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:gigabyte/m57sli&diff=4878Board:gigabyte/m57sli2007-09-04T10:03:53Z<p>Quux: /* Which board do you have? */ SOIC / SPI</p>
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<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:gigabyte/m57sli&diff=4877Board:gigabyte/m57sli2007-08-30T21:49:51Z<p>Quux: /* Which board do you have? */</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=4862Board:asus/a8n e2007-08-29T17:00:18Z<p>Quux: /* known issues */ MAC @ddr</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=File:A8n-e_hot_plug.jpg&diff=4861File:A8n-e hot plug.jpg2007-08-27T12:46:25Z<p>Quux: hot pluggable flash mems on ASUS board</p>
<hr />
<div>hot pluggable flash mems on ASUS board</div>Quuxhttps://www.coreboot.org/index.php?title=FAQ&diff=4860FAQ2007-08-27T11:04:42Z<p>Quux: /* Chip removal tools */ hot plug possible</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=4856Board:asus/a8n e2007-08-25T23:02:03Z<p>Quux: /* Before you begin */ hot plug bios , 8 MBit working</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:gigabyte/m57sli&diff=4854Board:gigabyte/m57sli2007-08-25T08:22:53Z<p>Quux: /* TODO */</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:gigabyte/m57sli&diff=4853Board:gigabyte/m57sli2007-08-25T08:22:06Z<p>Quux: /* TODO */</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:gigabyte/m57sli&diff=4852Board:gigabyte/m57sli2007-08-25T08:21:27Z<p>Quux: /* TODO */</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:gigabyte/m57sli&diff=4851Board:gigabyte/m57sli2007-08-25T08:21:10Z<p>Quux: </p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Glossary&diff=4849Glossary2007-08-18T19:15:38Z<p>Quux: /* DSDT */</p>
<hr />
<div>== A ==<br />
<br />
=== ACPI ===<br />
The '''Advanced Configuration & Power Interface''' is an industry standard for letting the OS control power management.<br />
* http://www.acpi.info/<br />
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface<br />
* http://kernelslacker.livejournal.com/88243.html acpitool to generate a C source (see mailing list also)<br />
<br />
=== AGP ===<br />
'''Advanced Graphics Port'''<br />
* http://en.wikipedia.org/wiki/AGP<br />
<br />
=== AGP Aperture ===<br />
The memory range that is set aside for AGP access.<br />
* http://en.wikipedia.org/wiki/AGP<br />
<br />
=== AHCI ===<br />
The '''Advanced Host Controller Interface'''. Describes the register-level interface for a SATA host controller.<br />
* http://en.wikipedia.org/wiki/AHCI<br />
* http://www.intel.com/technology/serialata/ahci.htm<br />
<br />
=== APIC ===<br />
'''Advanced Programmable Interrupt Controller'''. An advanced version of a [[Glossary#PIC|PIC]] that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs are CPU-bound, IO-APICs are bridge-bound.<br />
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller<br />
* http://osdev.berlios.de/pic.html<br />
<br />
<br />
== B ==<br />
<br />
=== BAR ===<br />
Base Address Register (on PCI device).<br />
<br />
=== BIOS ===<br />
Basic Input/Output System.<br />
<br />
<br />
== C ==<br />
<br />
=== CAR === <br />
Cache as RAM.<br />
<br />
=== CMOS === <br />
Complementary metal oxyde semiconductor.<br />
<br />
=== CPU ===<br />
Central processing unit (e.g. an Athlon64)<br />
<br />
== D ==<br />
<br />
=== DCR ===<br />
Decode Control Register.<br />
<br />
=== DID ===<br />
Device ID, a way of identifying the hardware in question. See [[Glossary#VID|VID]] for more info.<br />
<br />
=== DMA ===<br />
Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card.<br />
DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.<br />
* http://en.wikipedia.org/wiki/Direct_memory_access<br />
<br />
=== DSDT ===<br />
Differentiated System Descriptor Table, generated by BIOS and necessary for ACPI, see mailing list also. Implementation of ACPI needs to be done in a "cleanroom" development process to avoid legal issues.<br />
* http://acpi.sourceforge.net/dsdt/index.php<br />
<br />
== E ==<br />
<br />
=== EEPROM ===<br />
Electrically erasable programmable ROM (common mistake: electrical erasable programmable ROM).<br />
<br />
=== EHCI ===<br />
Enhanced Host Controller Interface (USB host controller).<br />
<br />
== F ==<br />
<br />
=== Flashing ===<br />
Flashing means writing of flash memory. The BIOS on modern mainboards is stored in a flash memory chip, which can be 128 Kilobytes to 4 Megabytes big.<br />
<br />
=== Framebuffer ===<br />
The '''Framebuffer''' is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen.<br />
A framebuffer is either:<br />
* Off-screen, meaning that writes to the framebuffer don't appear on the visible screen<br />
* On-screen, meaning that the framebuffer is directly coupled to the visible display<br />
<br />
* http://en.wikipedia.org/wiki/Framebuffer<br />
<br />
<br />
== G ==<br />
<br />
=== GART ===<br />
Graphics Address Relocation Table.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
<br />
=== GATT === <br />
Graphics Aperture Translation Table.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
<br />
=== GPIO ===<br />
General Purpose Input/Output.<br />
* http://en.wikipedia.org/wiki/GPIO<br />
<br />
=== GSoC ===<br />
[[GSoC|Google Summer of Code]].<br />
<br />
== H ==<br />
<br />
=== Hypertransport ===<br />
A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.<br />
* http://en.wikipedia.org/wiki/Hypertransport<br />
* http://www.hypertransport.org<br />
<br />
<br />
== I ==<br />
<br />
=== I2C ===<br />
'''Inter-Integrated-Circuit''', a bidirectional 2-wire bus for efficient inter-IC control.<br />
* http://www.esacademy.com/faq/i2c/index.htm<br />
<br />
=== IDSEL/AD ===<br />
Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?<br />
* http://www.techfest.com/hardware/bus/pci.htm<br />
* http://www.fpga4fun.com/PCI4.html<br />
<br />
=== IRQ ===<br />
Interrupt ReQuest (Handler).<br />
<br />
<br />
== J ==<br />
<br />
=== JTAG ===<br />
Debugging and test 4-wire interface named after an organization which defined it.<br />
<br />
== L ==<br />
<br />
=== LAR ===<br />
is the LinuxBIOS [[LAR_Design|Archiver]]. It is a small utility that we use to create and change LinuxBIOS images and their modules.<br />
<br />
=== LPC ===<br />
'''Low Pin Count''', an interface aimed at replacing the ISA bus.<br />
* http://www.intel.com/design/chipsets/industry/lpc.htm<br />
<br />
=== LRU ===<br />
'''Least Recently Used''', a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.<br />
* http://computer.laborlawtalk.com/Least%20Recently%20Used<br />
<br />
== M ==<br />
<br />
=== MII ===<br />
'''Media Independent Interface'''. This is a chip commonly found on ethernet devices, together with a PHY.<br />
* http://en.wikipedia.org/wiki/MII<br />
<br />
=== MMIO ===<br />
'''Memory-mapped I/O''' and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.<br />
* http://en.wikipedia.org/wiki/MMIO<br />
<br />
=== MPTable ===<br />
'''Multi Processor Table'''. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.<br />
* http://www.uruk.org/mps/<br />
* http://www.intel.com/design/pentium/datashts/242016.htm<br />
<br />
=== MTRR ===<br />
'''Memory Type Range Register'''. This can be used to control the way a processor accesses memory ranges.<br />
* http://en.wikipedia.org/wiki/MTRR<br />
<br />
<br />
== O ==<br />
<br />
=== OHCI ===<br />
'''Open Host Controller Interface'''. IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel).<br />
* http://en.wikipedia.org/wiki/Ohci<br />
* http://developer.intel.com/technology/1394/download/ohci_11.htm<br />
<br />
<br />
== P ==<br />
<br />
=== PAM ===<br />
'''Programmable Attribute Map'''. Hardware registers that describe how certain memory areas are accessed. The '''BIOS''' areas have a flash chip mapped on top of a piece of memory. By changing the '''PAM''' registers, accesses to these memory areas can be mapped to either the RAM or the flash device. '''Shadowing''' is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the '''PAM''' registers are part of the southbridge of a system.<br />
<br />
=== PAT ===<br />
'''Page Attribute Table'''. Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.<br />
* http://www.intel.com/design/pentium4/manuals/index_new.htm<br />
* http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10<br />
<br />
=== PAT ===<br />
Performance Acceleration Technology.<br />
* http://www.intel.com/design/chipsets/pat.htm<br />
<br />
=== PCI ===<br />
Peripheral Component Interconnect.<br />
* http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect<br />
<br />
=== PCI Configuration Space ===<br />
* http://en.wikipedia.org/wiki/PCI_Configuration_Space<br />
* http://www.techfest.com/hardware/bus/pci.htm<br />
<br />
=== PCI Express / PCIe ===<br />
* http://en.wikipedia.org/wiki/Pci_express<br />
<br />
=== PHY ===<br />
'''PHY layer device'''. A device that provides low level access to the physical layer.<br />
* http://en.wikipedia.org/wiki/PHY<br />
* http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer<br />
<br />
=== PIC ===<br />
A '''Programmable Interrupt Controller''' is a device to control peripheral devices, offloading the main CPU.<br />
* http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller<br />
* http://www.interq.or.jp/japan/se-inoue/e_pic1.htm<br />
<br />
=== PIO ===<br />
'''Programmed Input/Output''' interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.<br />
* http://en.wikipedia.org/wiki/Programmed_input/output<br />
<br />
=== PIR ===<br />
Programmable Interrupt Routing?<br />
<br />
=== PIRQ ===<br />
PCI IRQ routing table,<br />
* http://www.microsoft.com/whdc/archive/pciirq.mspx<br />
* http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm<br />
* Interesting tool?: https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view<br />
<br />
=== PLCC ===<br />
'''Plastic Leaded Chip Carrier''', a square surface-mount chip package.<br />
* http://www.webopedia.com/TERM/P/PLCC.html<br />
<br />
=== PLL ===<br />
'''Phase Locked Loop''' is a device to keep (electrical) signals synchronised throughout the system.<br />
* http://en.wikipedia.org/wiki/PLL<br />
<br />
=== POST ===<br />
The '''Power On Self Test''' is a test to check that devices the computer will rely on are functioning, and initializes devices.<br />
* http://en.wikipedia.org/wiki/Power-on_self_test<br />
<br />
== R ==<br />
<br />
=== RDMA ===<br />
'''Remote Direct Memory Access''' is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.<br />
* http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access<br />
<br />
=== RCS ===<br />
Revision control systems.<br />
<br />
== S ==<br />
<br />
=== SB ===<br />
'''Southbridge'''. Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...<br />
<br />
=== SBA ===<br />
SideBand Addressing.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
<br />
=== Shadow RAM ===<br />
RAM which content is copied from ROM residing at the same address for speedup purposes.<br />
<br />
=== SIO ===<br />
Serial Input/Output.<br />
* http://www.acronymfinder.com/af-query.asp?String=off&Acronym=sio&Find=Find&sourceid=mozilla-search<br />
<br />
=== SMBus ===<br />
The '''System Management Bus''' is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.<br />
* http://www.smbus.org/<br />
* http://www.computer-dictionary-online.org/index.asp?q=System%20Management%20Bus<br />
<br />
=== SMM ===<br />
'''System Management Mode'''. Processor mode that is mainly used for power management purposes.<br />
<br />
=== SMRAM ===<br />
System Management Random Access Memory.<br />
<br />
=== SPD ===<br />
'''Serial Presence Detect'''. On every (?) memory module there's an EPROM that provides the BIOS with information on how to properly configure the memory module.<br />
* http://www.simmtester.com/page/news/showpubnews.asp?num=101<br />
<br />
=== SPI ===<br />
The '''Serial Peripheral Interface Bus''' is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.<br />
* http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus<br />
<br />
=== SuperIO ===<br />
The '''SuperIO''' is the chip that provides floppy, serial and parallel functionality/ports.<br />
* http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html<br />
<br />
<br />
== T ==<br />
<br />
=== TLB ===<br />
'''Translation Lookaside Buffer'''. The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1<br />
<br />
<br />
== U ==<br />
<br />
=== UC ===<br />
Strong '''UnCacheable'''. Memory type setting in MTRR/PAT.<br />
<br />
=== UC ===<br />
'''UnCacheable'''. Memory type setting in MTRR/PAT.<br />
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3<br />
<br />
=== UHCI ===<br />
'''Universal Host Controller Interface'''. USB standard.<br />
* http://en.wikipedia.org/wiki/UHCI<br />
* http://developer.intel.com/technology/usb/uhci11d.htm<br />
<br />
<br />
== V ==<br />
<br />
=== VGAcon ===<br />
The purpose of the '''VGAcon''' (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students FPGA project).<br />
* http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm<br />
<br />
=== VID ===<br />
'''Vendor ID''', a way of identifying the hardware manufacturer.<br />
* http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx<br />
* http://pciids.sourceforge.net/<br />
A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.<br />
<br />
=== VMEBus ===<br />
'''VERSAmodule Eurocard Bus''' or '''Versa Module Europa Bus'''. A computer bus originally developed for the Motorola 68000.<br />
* http://en.wikipedia.org/wiki/VMEbus<br />
<br />
== W ==<br />
<br />
=== WB ===<br />
Write-Back. Memory type setting in MTRR/PAT.<br />
<br />
=== WC ===<br />
Write-Combining. Memory type setting in MTRR/PAT.<br />
<br />
=== WP ===<br />
Write Protected. Memory type setting in MTRR/PAT.<br />
<br />
=== WT ===<br />
Write-Through. Memory type setting in MTRR/PAT.<br />
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3</div>Quuxhttps://www.coreboot.org/index.php?title=Glossary&diff=4848Glossary2007-08-18T19:15:20Z<p>Quux: /* DSDT */ clean room</p>
<hr />
<div>== A ==<br />
<br />
=== ACPI ===<br />
The '''Advanced Configuration & Power Interface''' is an industry standard for letting the OS control power management.<br />
* http://www.acpi.info/<br />
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface<br />
* http://kernelslacker.livejournal.com/88243.html acpitool to generate a C source (see mailing list also)<br />
<br />
=== AGP ===<br />
'''Advanced Graphics Port'''<br />
* http://en.wikipedia.org/wiki/AGP<br />
<br />
=== AGP Aperture ===<br />
The memory range that is set aside for AGP access.<br />
* http://en.wikipedia.org/wiki/AGP<br />
<br />
=== AHCI ===<br />
The '''Advanced Host Controller Interface'''. Describes the register-level interface for a SATA host controller.<br />
* http://en.wikipedia.org/wiki/AHCI<br />
* http://www.intel.com/technology/serialata/ahci.htm<br />
<br />
=== APIC ===<br />
'''Advanced Programmable Interrupt Controller'''. An advanced version of a [[Glossary#PIC|PIC]] that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs are CPU-bound, IO-APICs are bridge-bound.<br />
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller<br />
* http://osdev.berlios.de/pic.html<br />
<br />
<br />
== B ==<br />
<br />
=== BAR ===<br />
Base Address Register (on PCI device).<br />
<br />
=== BIOS ===<br />
Basic Input/Output System.<br />
<br />
<br />
== C ==<br />
<br />
=== CAR === <br />
Cache as RAM.<br />
<br />
=== CMOS === <br />
Complementary metal oxyde semiconductor.<br />
<br />
=== CPU ===<br />
Central processing unit (e.g. an Athlon64)<br />
<br />
== D ==<br />
<br />
=== DCR ===<br />
Decode Control Register.<br />
<br />
=== DID ===<br />
Device ID, a way of identifying the hardware in question. See [[Glossary#VID|VID]] for more info.<br />
<br />
=== DMA ===<br />
Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card.<br />
DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.<br />
* http://en.wikipedia.org/wiki/Direct_memory_access<br />
<br />
=== DSDT ===<br />
Differentiated System Descriptor Table, generated by BIOS and necessary for ACPI, see mailing list also. Implementation of ACPI for the needs to be done in a "cleanroom" development process to avoid legal issues.<br />
* http://acpi.sourceforge.net/dsdt/index.php<br />
<br />
== E ==<br />
<br />
=== EEPROM ===<br />
Electrically erasable programmable ROM (common mistake: electrical erasable programmable ROM).<br />
<br />
=== EHCI ===<br />
Enhanced Host Controller Interface (USB host controller).<br />
<br />
== F ==<br />
<br />
=== Flashing ===<br />
Flashing means writing of flash memory. The BIOS on modern mainboards is stored in a flash memory chip, which can be 128 Kilobytes to 4 Megabytes big.<br />
<br />
=== Framebuffer ===<br />
The '''Framebuffer''' is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen.<br />
A framebuffer is either:<br />
* Off-screen, meaning that writes to the framebuffer don't appear on the visible screen<br />
* On-screen, meaning that the framebuffer is directly coupled to the visible display<br />
<br />
* http://en.wikipedia.org/wiki/Framebuffer<br />
<br />
<br />
== G ==<br />
<br />
=== GART ===<br />
Graphics Address Relocation Table.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
<br />
=== GATT === <br />
Graphics Aperture Translation Table.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
<br />
=== GPIO ===<br />
General Purpose Input/Output.<br />
* http://en.wikipedia.org/wiki/GPIO<br />
<br />
=== GSoC ===<br />
[[GSoC|Google Summer of Code]].<br />
<br />
== H ==<br />
<br />
=== Hypertransport ===<br />
A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.<br />
* http://en.wikipedia.org/wiki/Hypertransport<br />
* http://www.hypertransport.org<br />
<br />
<br />
== I ==<br />
<br />
=== I2C ===<br />
'''Inter-Integrated-Circuit''', a bidirectional 2-wire bus for efficient inter-IC control.<br />
* http://www.esacademy.com/faq/i2c/index.htm<br />
<br />
=== IDSEL/AD ===<br />
Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?<br />
* http://www.techfest.com/hardware/bus/pci.htm<br />
* http://www.fpga4fun.com/PCI4.html<br />
<br />
=== IRQ ===<br />
Interrupt ReQuest (Handler).<br />
<br />
<br />
== J ==<br />
<br />
=== JTAG ===<br />
Debugging and test 4-wire interface named after an organization which defined it.<br />
<br />
== L ==<br />
<br />
=== LAR ===<br />
is the LinuxBIOS [[LAR_Design|Archiver]]. It is a small utility that we use to create and change LinuxBIOS images and their modules.<br />
<br />
=== LPC ===<br />
'''Low Pin Count''', an interface aimed at replacing the ISA bus.<br />
* http://www.intel.com/design/chipsets/industry/lpc.htm<br />
<br />
=== LRU ===<br />
'''Least Recently Used''', a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.<br />
* http://computer.laborlawtalk.com/Least%20Recently%20Used<br />
<br />
== M ==<br />
<br />
=== MII ===<br />
'''Media Independent Interface'''. This is a chip commonly found on ethernet devices, together with a PHY.<br />
* http://en.wikipedia.org/wiki/MII<br />
<br />
=== MMIO ===<br />
'''Memory-mapped I/O''' and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.<br />
* http://en.wikipedia.org/wiki/MMIO<br />
<br />
=== MPTable ===<br />
'''Multi Processor Table'''. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.<br />
* http://www.uruk.org/mps/<br />
* http://www.intel.com/design/pentium/datashts/242016.htm<br />
<br />
=== MTRR ===<br />
'''Memory Type Range Register'''. This can be used to control the way a processor accesses memory ranges.<br />
* http://en.wikipedia.org/wiki/MTRR<br />
<br />
<br />
== O ==<br />
<br />
=== OHCI ===<br />
'''Open Host Controller Interface'''. IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel).<br />
* http://en.wikipedia.org/wiki/Ohci<br />
* http://developer.intel.com/technology/1394/download/ohci_11.htm<br />
<br />
<br />
== P ==<br />
<br />
=== PAM ===<br />
'''Programmable Attribute Map'''. Hardware registers that describe how certain memory areas are accessed. The '''BIOS''' areas have a flash chip mapped on top of a piece of memory. By changing the '''PAM''' registers, accesses to these memory areas can be mapped to either the RAM or the flash device. '''Shadowing''' is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the '''PAM''' registers are part of the southbridge of a system.<br />
<br />
=== PAT ===<br />
'''Page Attribute Table'''. Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.<br />
* http://www.intel.com/design/pentium4/manuals/index_new.htm<br />
* http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10<br />
<br />
=== PAT ===<br />
Performance Acceleration Technology.<br />
* http://www.intel.com/design/chipsets/pat.htm<br />
<br />
=== PCI ===<br />
Peripheral Component Interconnect.<br />
* http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect<br />
<br />
=== PCI Configuration Space ===<br />
* http://en.wikipedia.org/wiki/PCI_Configuration_Space<br />
* http://www.techfest.com/hardware/bus/pci.htm<br />
<br />
=== PCI Express / PCIe ===<br />
* http://en.wikipedia.org/wiki/Pci_express<br />
<br />
=== PHY ===<br />
'''PHY layer device'''. A device that provides low level access to the physical layer.<br />
* http://en.wikipedia.org/wiki/PHY<br />
* http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer<br />
<br />
=== PIC ===<br />
A '''Programmable Interrupt Controller''' is a device to control peripheral devices, offloading the main CPU.<br />
* http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller<br />
* http://www.interq.or.jp/japan/se-inoue/e_pic1.htm<br />
<br />
=== PIO ===<br />
'''Programmed Input/Output''' interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.<br />
* http://en.wikipedia.org/wiki/Programmed_input/output<br />
<br />
=== PIR ===<br />
Programmable Interrupt Routing?<br />
<br />
=== PIRQ ===<br />
PCI IRQ routing table,<br />
* http://www.microsoft.com/whdc/archive/pciirq.mspx<br />
* http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm<br />
* Interesting tool?: https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view<br />
<br />
=== PLCC ===<br />
'''Plastic Leaded Chip Carrier''', a square surface-mount chip package.<br />
* http://www.webopedia.com/TERM/P/PLCC.html<br />
<br />
=== PLL ===<br />
'''Phase Locked Loop''' is a device to keep (electrical) signals synchronised throughout the system.<br />
* http://en.wikipedia.org/wiki/PLL<br />
<br />
=== POST ===<br />
The '''Power On Self Test''' is a test to check that devices the computer will rely on are functioning, and initializes devices.<br />
* http://en.wikipedia.org/wiki/Power-on_self_test<br />
<br />
== R ==<br />
<br />
=== RDMA ===<br />
'''Remote Direct Memory Access''' is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.<br />
* http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access<br />
<br />
=== RCS ===<br />
Revision control systems.<br />
<br />
== S ==<br />
<br />
=== SB ===<br />
'''Southbridge'''. Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...<br />
<br />
=== SBA ===<br />
SideBand Addressing.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
<br />
=== Shadow RAM ===<br />
RAM which content is copied from ROM residing at the same address for speedup purposes.<br />
<br />
=== SIO ===<br />
Serial Input/Output.<br />
* http://www.acronymfinder.com/af-query.asp?String=off&Acronym=sio&Find=Find&sourceid=mozilla-search<br />
<br />
=== SMBus ===<br />
The '''System Management Bus''' is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.<br />
* http://www.smbus.org/<br />
* http://www.computer-dictionary-online.org/index.asp?q=System%20Management%20Bus<br />
<br />
=== SMM ===<br />
'''System Management Mode'''. Processor mode that is mainly used for power management purposes.<br />
<br />
=== SMRAM ===<br />
System Management Random Access Memory.<br />
<br />
=== SPD ===<br />
'''Serial Presence Detect'''. On every (?) memory module there's an EPROM that provides the BIOS with information on how to properly configure the memory module.<br />
* http://www.simmtester.com/page/news/showpubnews.asp?num=101<br />
<br />
=== SPI ===<br />
The '''Serial Peripheral Interface Bus''' is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.<br />
* http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus<br />
<br />
=== SuperIO ===<br />
The '''SuperIO''' is the chip that provides floppy, serial and parallel functionality/ports.<br />
* http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html<br />
<br />
<br />
== T ==<br />
<br />
=== TLB ===<br />
'''Translation Lookaside Buffer'''. The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1<br />
<br />
<br />
== U ==<br />
<br />
=== UC ===<br />
Strong '''UnCacheable'''. Memory type setting in MTRR/PAT.<br />
<br />
=== UC ===<br />
'''UnCacheable'''. Memory type setting in MTRR/PAT.<br />
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3<br />
<br />
=== UHCI ===<br />
'''Universal Host Controller Interface'''. USB standard.<br />
* http://en.wikipedia.org/wiki/UHCI<br />
* http://developer.intel.com/technology/usb/uhci11d.htm<br />
<br />
<br />
== V ==<br />
<br />
=== VGAcon ===<br />
The purpose of the '''VGAcon''' (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students FPGA project).<br />
* http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm<br />
<br />
=== VID ===<br />
'''Vendor ID''', a way of identifying the hardware manufacturer.<br />
* http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx<br />
* http://pciids.sourceforge.net/<br />
A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.<br />
<br />
=== VMEBus ===<br />
'''VERSAmodule Eurocard Bus''' or '''Versa Module Europa Bus'''. A computer bus originally developed for the Motorola 68000.<br />
* http://en.wikipedia.org/wiki/VMEbus<br />
<br />
== W ==<br />
<br />
=== WB ===<br />
Write-Back. Memory type setting in MTRR/PAT.<br />
<br />
=== WC ===<br />
Write-Combining. Memory type setting in MTRR/PAT.<br />
<br />
=== WP ===<br />
Write Protected. Memory type setting in MTRR/PAT.<br />
<br />
=== WT ===<br />
Write-Through. Memory type setting in MTRR/PAT.<br />
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3</div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=4831Board:asus/a8n e2007-08-16T23:05:44Z<p>Quux: /* Before you begin */ Biostar NF4-A9A</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Glossary&diff=4828Glossary2007-08-16T21:38:12Z<p>Quux: /* L */ LAR keeps getting mentioned in pipermail</p>
<hr />
<div>== A ==<br />
<br />
=== ACPI ===<br />
The '''Advanced Configuration & Power Interface''' is an industry standard for letting the OS control power management.<br />
* http://www.acpi.info/<br />
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface<br />
* http://kernelslacker.livejournal.com/88243.html acpitool to generate a C source (see mailing list also)<br />
<br />
=== AGP ===<br />
'''Advanced Graphics Port'''<br />
* http://en.wikipedia.org/wiki/AGP<br />
<br />
=== AGP Aperture ===<br />
The memory range that is set aside for AGP access.<br />
* http://en.wikipedia.org/wiki/AGP<br />
<br />
=== AHCI ===<br />
The '''Advanced Host Controller Interface'''. Describes the register-level interface for a SATA host controller.<br />
* http://en.wikipedia.org/wiki/AHCI<br />
* http://www.intel.com/technology/serialata/ahci.htm<br />
<br />
=== APIC ===<br />
'''Advanced Programmable Interrupt Controller'''. An advanced version of a [[Glossary#PIC|PIC]] that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs are CPU-bound, IO-APICs are bridge-bound.<br />
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller<br />
* http://osdev.berlios.de/pic.html<br />
<br />
<br />
== B ==<br />
<br />
=== BAR ===<br />
Base Address Register (on PCI device).<br />
<br />
=== BIOS ===<br />
Basic Input/Output System.<br />
<br />
<br />
== C ==<br />
<br />
=== CAR === <br />
Cache as RAM.<br />
<br />
=== CMOS === <br />
Complementary metal oxyde semiconductor.<br />
<br />
=== CPU ===<br />
Central processing unit (e.g. an Athlon64)<br />
<br />
== D ==<br />
<br />
=== DCR ===<br />
Decode Control Register.<br />
<br />
=== DID ===<br />
Device ID, a way of identifying the hardware in question. See [[Glossary#VID|VID]] for more info.<br />
<br />
=== DMA ===<br />
Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card.<br />
DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.<br />
* http://en.wikipedia.org/wiki/Direct_memory_access<br />
<br />
=== DSDT ===<br />
Differentiated System Descriptor Table, generated by BIOS and necessary for ACPI, see mailing list also<br />
* http://acpi.sourceforge.net/dsdt/index.php<br />
<br />
== E ==<br />
<br />
=== EEPROM ===<br />
Electrically erasable programmable ROM (common mistake: electrical erasable programmable ROM).<br />
<br />
=== EHCI ===<br />
Enhanced Host Controller Interface (USB host controller).<br />
<br />
== F ==<br />
<br />
=== Flashing ===<br />
Flashing means writing of flash memory. The BIOS on modern mainboards is stored in a flash memory chip, which can be 128 Kilobytes to 4 Megabytes big.<br />
<br />
=== Framebuffer ===<br />
The '''Framebuffer''' is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen.<br />
A framebuffer is either:<br />
* Off-screen, meaning that writes to the framebuffer don't appear on the visible screen<br />
* On-screen, meaning that the framebuffer is directly coupled to the visible display<br />
<br />
* http://en.wikipedia.org/wiki/Framebuffer<br />
<br />
<br />
== G ==<br />
<br />
=== GART ===<br />
Graphics Address Relocation Table.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
<br />
=== GATT === <br />
Graphics Aperture Translation Table.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
<br />
=== GPIO ===<br />
General Purpose Input/Output.<br />
* http://en.wikipedia.org/wiki/GPIO<br />
<br />
=== GSoC ===<br />
[[GSoC|Google Summer of Code]].<br />
<br />
== H ==<br />
<br />
=== Hypertransport ===<br />
A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.<br />
* http://en.wikipedia.org/wiki/Hypertransport<br />
* http://www.hypertransport.org<br />
<br />
<br />
== I ==<br />
<br />
=== I2C ===<br />
'''Inter-Integrated-Circuit''', a bidirectional 2-wire bus for efficient inter-IC control.<br />
* http://www.esacademy.com/faq/i2c/index.htm<br />
<br />
=== IDSEL/AD ===<br />
Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?<br />
* http://www.techfest.com/hardware/bus/pci.htm<br />
* http://www.fpga4fun.com/PCI4.html<br />
<br />
=== IRQ ===<br />
Interrupt ReQuest (Handler).<br />
<br />
<br />
== J ==<br />
<br />
=== JTAG ===<br />
Debugging and test 4-wire interface named after an organization which defined it.<br />
<br />
== L ==<br />
<br />
=== LAR ===<br />
is the LinuxBIOS [[LAR_Design|Archiver]]. It is a small utility that we use to create and change LinuxBIOS images and their modules.<br />
<br />
=== LPC ===<br />
'''Low Pin Count''', an interface aimed at replacing the ISA bus.<br />
* http://www.intel.com/design/chipsets/industry/lpc.htm<br />
<br />
=== LRU ===<br />
'''Least Recently Used''', a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.<br />
* http://computer.laborlawtalk.com/Least%20Recently%20Used<br />
<br />
== M ==<br />
<br />
=== MII ===<br />
'''Media Independent Interface'''. This is a chip commonly found on ethernet devices, together with a PHY.<br />
* http://en.wikipedia.org/wiki/MII<br />
<br />
=== MMIO ===<br />
'''Memory-mapped I/O''' and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.<br />
* http://en.wikipedia.org/wiki/MMIO<br />
<br />
=== MPTable ===<br />
'''Multi Processor Table'''. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.<br />
* http://www.uruk.org/mps/<br />
* http://www.intel.com/design/pentium/datashts/242016.htm<br />
<br />
=== MTRR ===<br />
'''Memory Type Range Register'''. This can be used to control the way a processor accesses memory ranges.<br />
* http://en.wikipedia.org/wiki/MTRR<br />
<br />
<br />
== O ==<br />
<br />
=== OHCI ===<br />
'''Open Host Controller Interface'''. IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel).<br />
* http://en.wikipedia.org/wiki/Ohci<br />
* http://developer.intel.com/technology/1394/download/ohci_11.htm<br />
<br />
<br />
== P ==<br />
<br />
=== PAM ===<br />
'''Programmable Attribute Map'''. Hardware registers that describe how certain memory areas are accessed. The '''BIOS''' areas have a flash chip mapped on top of a piece of memory. By changing the '''PAM''' registers, accesses to these memory areas can be mapped to either the RAM or the flash device. '''Shadowing''' is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the '''PAM''' registers are part of the southbridge of a system.<br />
<br />
=== PAT ===<br />
'''Page Attribute Table'''. Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.<br />
* http://www.intel.com/design/pentium4/manuals/index_new.htm<br />
* http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10<br />
<br />
=== PAT ===<br />
Performance Acceleration Technology.<br />
* http://www.intel.com/design/chipsets/pat.htm<br />
<br />
=== PCI ===<br />
Peripheral Component Interconnect.<br />
* http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect<br />
<br />
=== PCI Configuration Space ===<br />
* http://en.wikipedia.org/wiki/PCI_Configuration_Space<br />
* http://www.techfest.com/hardware/bus/pci.htm<br />
<br />
=== PCI Express / PCIe ===<br />
* http://en.wikipedia.org/wiki/Pci_express<br />
<br />
=== PHY ===<br />
'''PHY layer device'''. A device that provides low level access to the physical layer.<br />
* http://en.wikipedia.org/wiki/PHY<br />
* http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer<br />
<br />
=== PIC ===<br />
A '''Programmable Interrupt Controller''' is a device to control peripheral devices, offloading the main CPU.<br />
* http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller<br />
* http://www.interq.or.jp/japan/se-inoue/e_pic1.htm<br />
<br />
=== PIO ===<br />
'''Programmed Input/Output''' interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.<br />
* http://en.wikipedia.org/wiki/Programmed_input/output<br />
<br />
=== PIR ===<br />
Programmable Interrupt Routing?<br />
<br />
=== PIRQ ===<br />
PCI IRQ routing table,<br />
* http://www.microsoft.com/whdc/archive/pciirq.mspx<br />
* http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm<br />
* Interesting tool?: https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view<br />
<br />
=== PLCC ===<br />
'''Plastic Leaded Chip Carrier''', a square surface-mount chip package.<br />
* http://www.webopedia.com/TERM/P/PLCC.html<br />
<br />
=== PLL ===<br />
'''Phase Locked Loop''' is a device to keep (electrical) signals synchronised throughout the system.<br />
* http://en.wikipedia.org/wiki/PLL<br />
<br />
=== POST ===<br />
The '''Power On Self Test''' is a test to check that devices the computer will rely on are functioning, and initializes devices.<br />
* http://en.wikipedia.org/wiki/Power-on_self_test<br />
<br />
== R ==<br />
<br />
=== RDMA ===<br />
'''Remote Direct Memory Access''' is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.<br />
* http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access<br />
<br />
=== RCS ===<br />
Revision control systems.<br />
<br />
== S ==<br />
<br />
=== SB ===<br />
'''Southbridge'''. Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...<br />
<br />
=== SBA ===<br />
SideBand Addressing.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
<br />
=== Shadow RAM ===<br />
RAM which content is copied from ROM residing at the same address for speedup purposes.<br />
<br />
=== SIO ===<br />
Serial Input/Output.<br />
* http://www.acronymfinder.com/af-query.asp?String=off&Acronym=sio&Find=Find&sourceid=mozilla-search<br />
<br />
=== SMBus ===<br />
The '''System Management Bus''' is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.<br />
* http://www.smbus.org/<br />
* http://www.computer-dictionary-online.org/index.asp?q=System%20Management%20Bus<br />
<br />
=== SMM ===<br />
'''System Management Mode'''. Processor mode that is mainly used for power management purposes.<br />
<br />
=== SMRAM ===<br />
System Management Random Access Memory.<br />
<br />
=== SPD ===<br />
'''Serial Presence Detect'''. On every (?) memory module there's an EPROM that provides the BIOS with information on how to properly configure the memory module.<br />
* http://www.simmtester.com/page/news/showpubnews.asp?num=101<br />
<br />
=== SPI ===<br />
The '''Serial Peripheral Interface Bus''' is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.<br />
* http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus<br />
<br />
=== SuperIO ===<br />
The '''SuperIO''' is the chip that provides floppy, serial and parallel functionality/ports.<br />
* http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html<br />
<br />
<br />
== T ==<br />
<br />
=== TLB ===<br />
'''Translation Lookaside Buffer'''. The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1<br />
<br />
<br />
== U ==<br />
<br />
=== UC ===<br />
Strong '''UnCacheable'''. Memory type setting in MTRR/PAT.<br />
<br />
=== UC ===<br />
'''UnCacheable'''. Memory type setting in MTRR/PAT.<br />
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3<br />
<br />
=== UHCI ===<br />
'''Universal Host Controller Interface'''. USB standard.<br />
* http://en.wikipedia.org/wiki/UHCI<br />
* http://developer.intel.com/technology/usb/uhci11d.htm<br />
<br />
<br />
== V ==<br />
<br />
=== VGAcon ===<br />
The purpose of the '''VGAcon''' (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students FPGA project).<br />
* http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm<br />
<br />
=== VID ===<br />
'''Vendor ID''', a way of identifying the hardware manufacturer.<br />
* http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx<br />
* http://pciids.sourceforge.net/<br />
A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.<br />
<br />
=== VMEBus ===<br />
'''VERSAmodule Eurocard Bus''' or '''Versa Module Europa Bus'''. A computer bus originally developed for the Motorola 68000.<br />
* http://en.wikipedia.org/wiki/VMEbus<br />
<br />
== W ==<br />
<br />
=== WB ===<br />
Write-Back. Memory type setting in MTRR/PAT.<br />
<br />
=== WC ===<br />
Write-Combining. Memory type setting in MTRR/PAT.<br />
<br />
=== WP ===<br />
Write Protected. Memory type setting in MTRR/PAT.<br />
<br />
=== WT ===<br />
Write-Through. Memory type setting in MTRR/PAT.<br />
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3</div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=4825Board:asus/a8n e2007-08-16T14:45:03Z<p>Quux: /* Before you begin */ A8NE-FM/S started</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=4805Board:asus/a8n e2007-08-12T21:05:55Z<p>Quux: /* Before you begin */</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=4802Board:asus/a8n e2007-08-12T14:19:13Z<p>Quux: /* Before you begin */</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=4801Board:asus/a8n e2007-08-12T14:18:37Z<p>Quux: /* Before you begin */ SST49LF004B</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Talk:ASUS_A8N-E&diff=4800Talk:ASUS A8N-E2007-08-12T12:23:27Z<p>Quux: New page: there is an OEM board out the Fujitsu Siemens A8NE-FM/S , which seems to have different board layout and different, incompatible legacy BIOS to A8N-E. Looks like it has two more sockets fo...</p>
<hr />
<div>there is an OEM board out the Fujitsu Siemens A8NE-FM/S , which seems to have different board layout and different, incompatible legacy BIOS to A8N-E.<br />
Looks like it has two more sockets for sth.. there are reports that those mb get bricked when ASUS BIOS is flashed into them. The bios socket is at a different position.</div>Quuxhttps://www.coreboot.org/index.php?title=Glossary&diff=4798Glossary2007-08-12T04:31:35Z<p>Quux: /* D */ dsdt</p>
<hr />
<div>== A ==<br />
<br />
=== ACPI ===<br />
The '''Advanced Configuration & Power Interface''' is an industry standard for letting the OS control power management.<br />
* http://www.acpi.info/<br />
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface<br />
* http://kernelslacker.livejournal.com/88243.html acpitool to generate a C source (see mailing list also)<br />
<br />
=== AGP ===<br />
'''Advanced Graphics Port'''<br />
* http://en.wikipedia.org/wiki/AGP<br />
<br />
=== AGP Aperture ===<br />
The memory range that is set aside for AGP access.<br />
* http://en.wikipedia.org/wiki/AGP<br />
<br />
=== AHCI ===<br />
The '''Advanced Host Controller Interface'''. Describes the register-level interface for a SATA host controller.<br />
* http://en.wikipedia.org/wiki/AHCI<br />
* http://www.intel.com/technology/serialata/ahci.htm<br />
<br />
=== APIC ===<br />
'''Advanced Programmable Interrupt Controller'''. An advanced version of a [[Glossary#PIC|PIC]] that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs are CPU-bound, IO-APICs are bridge-bound.<br />
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller<br />
* http://osdev.berlios.de/pic.html<br />
<br />
<br />
== B ==<br />
<br />
=== BAR ===<br />
Base Address Register (on PCI device).<br />
<br />
=== BIOS ===<br />
Basic Input/Output System.<br />
<br />
<br />
== C ==<br />
<br />
=== CAR === <br />
Cache as RAM.<br />
<br />
=== CMOS === <br />
Complementary metal oxyde semiconductor.<br />
<br />
=== CPU ===<br />
Central processing unit (e.g. an Athlon64)<br />
<br />
== D ==<br />
<br />
=== DCR ===<br />
Decode Control Register.<br />
<br />
=== DID ===<br />
Device ID, a way of identifying the hardware in question. See [[Glossary#VID|VID]] for more info.<br />
<br />
=== DMA ===<br />
Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card.<br />
DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.<br />
* http://en.wikipedia.org/wiki/Direct_memory_access<br />
<br />
=== DSDT ===<br />
Differentiated System Descriptor Table, generated by BIOS and necessary for ACPI, see mailing list also<br />
* http://acpi.sourceforge.net/dsdt/index.php<br />
<br />
== E ==<br />
<br />
=== EEPROM ===<br />
Electrically erasable programmable ROM (common mistake: electrical erasable programmable ROM).<br />
<br />
=== EHCI ===<br />
Enhanced Host Controller Interface (USB host controller).<br />
<br />
== F ==<br />
<br />
=== Flashing ===<br />
Flashing means writing of flash memory. The BIOS on modern mainboards is stored in a flash memory chip, which can be 128 Kilobytes to 4 Megabytes big.<br />
<br />
=== Framebuffer ===<br />
The '''Framebuffer''' is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen.<br />
A framebuffer is either:<br />
* Off-screen, meaning that writes to the framebuffer don't appear on the visible screen<br />
* On-screen, meaning that the framebuffer is directly coupled to the visible display<br />
<br />
* http://en.wikipedia.org/wiki/Framebuffer<br />
<br />
<br />
== G ==<br />
<br />
=== GART ===<br />
Graphics Address Relocation Table.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
<br />
=== GATT === <br />
Graphics Aperture Translation Table.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
<br />
=== GPIO ===<br />
General Purpose Input/Output.<br />
* http://en.wikipedia.org/wiki/GPIO<br />
<br />
=== GSoC ===<br />
[[GSoC|Google Summer of Code]].<br />
<br />
== H ==<br />
<br />
=== Hypertransport ===<br />
A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.<br />
* http://en.wikipedia.org/wiki/Hypertransport<br />
* http://www.hypertransport.org<br />
<br />
<br />
== I ==<br />
<br />
=== I2C ===<br />
'''Inter-Integrated-Circuit''', a bidirectional 2-wire bus for efficient inter-IC control.<br />
* http://www.esacademy.com/faq/i2c/index.htm<br />
<br />
=== IDSEL/AD ===<br />
Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?<br />
* http://www.techfest.com/hardware/bus/pci.htm<br />
* http://www.fpga4fun.com/PCI4.html<br />
<br />
=== IRQ ===<br />
Interrupt ReQuest (Handler).<br />
<br />
<br />
== J ==<br />
<br />
=== JTAG ===<br />
Debugging and test 4-wire interface named after an organization which defined it.<br />
<br />
== L ==<br />
<br />
=== LPC ===<br />
'''Low Pin Count''', an interface aimed at replacing the ISA bus.<br />
* http://www.intel.com/design/chipsets/industry/lpc.htm<br />
<br />
=== LRU ===<br />
'''Least Recently Used''', a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.<br />
* http://computer.laborlawtalk.com/Least%20Recently%20Used<br />
<br />
<br />
== M ==<br />
<br />
=== MII ===<br />
'''Media Independent Interface'''. This is a chip commonly found on ethernet devices, together with a PHY.<br />
* http://en.wikipedia.org/wiki/MII<br />
<br />
=== MMIO ===<br />
'''Memory-mapped I/O''' and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.<br />
* http://en.wikipedia.org/wiki/MMIO<br />
<br />
=== MPTable ===<br />
'''Multi Processor Table'''. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.<br />
* http://www.uruk.org/mps/<br />
* http://www.intel.com/design/pentium/datashts/242016.htm<br />
<br />
=== MTRR ===<br />
'''Memory Type Range Register'''. This can be used to control the way a processor accesses memory ranges.<br />
* http://en.wikipedia.org/wiki/MTRR<br />
<br />
<br />
== O ==<br />
<br />
=== OHCI ===<br />
'''Open Host Controller Interface'''. IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel).<br />
* http://en.wikipedia.org/wiki/Ohci<br />
* http://developer.intel.com/technology/1394/download/ohci_11.htm<br />
<br />
<br />
== P ==<br />
<br />
=== PAM ===<br />
'''Programmable Attribute Map'''. Hardware registers that describe how certain memory areas are accessed. The '''BIOS''' areas have a flash chip mapped on top of a piece of memory. By changing the '''PAM''' registers, accesses to these memory areas can be mapped to either the RAM or the flash device. '''Shadowing''' is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the '''PAM''' registers are part of the southbridge of a system.<br />
<br />
=== PAT ===<br />
'''Page Attribute Table'''. Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.<br />
* http://www.intel.com/design/pentium4/manuals/index_new.htm<br />
* http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10<br />
<br />
=== PAT ===<br />
Performance Acceleration Technology.<br />
* http://www.intel.com/design/chipsets/pat.htm<br />
<br />
=== PCI ===<br />
Peripheral Component Interconnect.<br />
* http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect<br />
<br />
=== PCI Configuration Space ===<br />
* http://en.wikipedia.org/wiki/PCI_Configuration_Space<br />
* http://www.techfest.com/hardware/bus/pci.htm<br />
<br />
=== PCI Express / PCIe ===<br />
* http://en.wikipedia.org/wiki/Pci_express<br />
<br />
=== PHY ===<br />
'''PHY layer device'''. A device that provides low level access to the physical layer.<br />
* http://en.wikipedia.org/wiki/PHY<br />
* http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer<br />
<br />
=== PIC ===<br />
A '''Programmable Interrupt Controller''' is a device to control peripheral devices, offloading the main CPU.<br />
* http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller<br />
* http://www.interq.or.jp/japan/se-inoue/e_pic1.htm<br />
<br />
=== PIO ===<br />
'''Programmed Input/Output''' interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.<br />
* http://en.wikipedia.org/wiki/Programmed_input/output<br />
<br />
=== PIR ===<br />
Programmable Interrupt Routing?<br />
<br />
=== PIRQ ===<br />
PCI IRQ routing table,<br />
* http://www.microsoft.com/whdc/archive/pciirq.mspx<br />
* http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm<br />
* Interesting tool?: https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view<br />
<br />
=== PLCC ===<br />
'''Plastic Leaded Chip Carrier''', a square surface-mount chip package.<br />
* http://www.webopedia.com/TERM/P/PLCC.html<br />
<br />
=== PLL ===<br />
'''Phase Locked Loop''' is a device to keep (electrical) signals synchronised throughout the system.<br />
* http://en.wikipedia.org/wiki/PLL<br />
<br />
=== POST ===<br />
The '''Power On Self Test''' is a test to check that devices the computer will rely on are functioning, and initializes devices.<br />
* http://en.wikipedia.org/wiki/Power-on_self_test<br />
<br />
== R ==<br />
<br />
=== RDMA ===<br />
'''Remote Direct Memory Access''' is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.<br />
* http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access<br />
<br />
=== RCS ===<br />
Revision control systems.<br />
<br />
== S ==<br />
<br />
=== SB ===<br />
'''Southbridge'''. Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...<br />
<br />
=== SBA ===<br />
SideBand Addressing.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
<br />
=== Shadow RAM ===<br />
RAM which content is copied from ROM residing at the same address for speedup purposes.<br />
<br />
=== SIO ===<br />
Serial Input/Output.<br />
* http://www.acronymfinder.com/af-query.asp?String=off&Acronym=sio&Find=Find&sourceid=mozilla-search<br />
<br />
=== SMBus ===<br />
The '''System Management Bus''' is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.<br />
* http://www.smbus.org/<br />
* http://www.computer-dictionary-online.org/index.asp?q=System%20Management%20Bus<br />
<br />
=== SMM ===<br />
'''System Management Mode'''. Processor mode that is mainly used for power management purposes.<br />
<br />
=== SMRAM ===<br />
System Management Random Access Memory.<br />
<br />
=== SPD ===<br />
'''Serial Presence Detect'''. On every (?) memory module there's an EPROM that provides the BIOS with information on how to properly configure the memory module.<br />
* http://www.simmtester.com/page/news/showpubnews.asp?num=101<br />
<br />
=== SPI ===<br />
The '''Serial Peripheral Interface Bus''' is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.<br />
* http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus<br />
<br />
=== SuperIO ===<br />
The '''SuperIO''' is the chip that provides floppy, serial and parallel functionality/ports.<br />
* http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html<br />
<br />
<br />
== T ==<br />
<br />
=== TLB ===<br />
'''Translation Lookaside Buffer'''. The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1<br />
<br />
<br />
== U ==<br />
<br />
=== UC ===<br />
Strong '''UnCacheable'''. Memory type setting in MTRR/PAT.<br />
<br />
=== UC ===<br />
'''UnCacheable'''. Memory type setting in MTRR/PAT.<br />
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3<br />
<br />
=== UHCI ===<br />
'''Universal Host Controller Interface'''. USB standard.<br />
* http://en.wikipedia.org/wiki/UHCI<br />
* http://developer.intel.com/technology/usb/uhci11d.htm<br />
<br />
<br />
== V ==<br />
<br />
=== VGAcon ===<br />
The purpose of the '''VGAcon''' (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students FPGA project).<br />
* http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm<br />
<br />
=== VID ===<br />
'''Vendor ID''', a way of identifying the hardware manufacturer.<br />
* http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx<br />
* http://pciids.sourceforge.net/<br />
A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.<br />
<br />
=== VMEBus ===<br />
'''VERSAmodule Eurocard Bus''' or '''Versa Module Europa Bus'''. A computer bus originally developed for the Motorola 68000.<br />
* http://en.wikipedia.org/wiki/VMEbus<br />
<br />
== W ==<br />
<br />
=== WB ===<br />
Write-Back. Memory type setting in MTRR/PAT.<br />
<br />
=== WC ===<br />
Write-Combining. Memory type setting in MTRR/PAT.<br />
<br />
=== WP ===<br />
Write Protected. Memory type setting in MTRR/PAT.<br />
<br />
=== WT ===<br />
Write-Through. Memory type setting in MTRR/PAT.<br />
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3</div>Quuxhttps://www.coreboot.org/index.php?title=Glossary&diff=4797Glossary2007-08-12T04:15:05Z<p>Quux: /* ACPI */ acpitool mentioned in mailing list</p>
<hr />
<div>== A ==<br />
<br />
=== ACPI ===<br />
The '''Advanced Configuration & Power Interface''' is an industry standard for letting the OS control power management.<br />
* http://www.acpi.info/<br />
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface<br />
* http://kernelslacker.livejournal.com/88243.html acpitool to generate a C source (see mailing list also)<br />
<br />
=== AGP ===<br />
'''Advanced Graphics Port'''<br />
* http://en.wikipedia.org/wiki/AGP<br />
<br />
=== AGP Aperture ===<br />
The memory range that is set aside for AGP access.<br />
* http://en.wikipedia.org/wiki/AGP<br />
<br />
=== AHCI ===<br />
The '''Advanced Host Controller Interface'''. Describes the register-level interface for a SATA host controller.<br />
* http://en.wikipedia.org/wiki/AHCI<br />
* http://www.intel.com/technology/serialata/ahci.htm<br />
<br />
=== APIC ===<br />
'''Advanced Programmable Interrupt Controller'''. An advanced version of a [[Glossary#PIC|PIC]] that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs are CPU-bound, IO-APICs are bridge-bound.<br />
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller<br />
* http://osdev.berlios.de/pic.html<br />
<br />
<br />
== B ==<br />
<br />
=== BAR ===<br />
Base Address Register (on PCI device).<br />
<br />
=== BIOS ===<br />
Basic Input/Output System.<br />
<br />
<br />
== C ==<br />
<br />
=== CAR === <br />
Cache as RAM.<br />
<br />
=== CMOS === <br />
Complementary metal oxyde semiconductor.<br />
<br />
=== CPU ===<br />
Central processing unit (e.g. an Athlon64)<br />
<br />
== D ==<br />
<br />
=== DCR ===<br />
Decode Control Register.<br />
<br />
=== DID ===<br />
Device ID, a way of identifying the hardware in question. See [[Glossary#VID|VID]] for more info.<br />
<br />
=== DMA ===<br />
Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card.<br />
DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.<br />
* http://en.wikipedia.org/wiki/Direct_memory_access<br />
<br />
== E ==<br />
<br />
=== EEPROM ===<br />
Electrically erasable programmable ROM (common mistake: electrical erasable programmable ROM).<br />
<br />
=== EHCI ===<br />
Enhanced Host Controller Interface (USB host controller).<br />
<br />
== F ==<br />
<br />
=== Flashing ===<br />
Flashing means writing of flash memory. The BIOS on modern mainboards is stored in a flash memory chip, which can be 128 Kilobytes to 4 Megabytes big.<br />
<br />
=== Framebuffer ===<br />
The '''Framebuffer''' is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen.<br />
A framebuffer is either:<br />
* Off-screen, meaning that writes to the framebuffer don't appear on the visible screen<br />
* On-screen, meaning that the framebuffer is directly coupled to the visible display<br />
<br />
* http://en.wikipedia.org/wiki/Framebuffer<br />
<br />
<br />
== G ==<br />
<br />
=== GART ===<br />
Graphics Address Relocation Table.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
<br />
=== GATT === <br />
Graphics Aperture Translation Table.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
<br />
=== GPIO ===<br />
General Purpose Input/Output.<br />
* http://en.wikipedia.org/wiki/GPIO<br />
<br />
=== GSoC ===<br />
[[GSoC|Google Summer of Code]].<br />
<br />
== H ==<br />
<br />
=== Hypertransport ===<br />
A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.<br />
* http://en.wikipedia.org/wiki/Hypertransport<br />
* http://www.hypertransport.org<br />
<br />
<br />
== I ==<br />
<br />
=== I2C ===<br />
'''Inter-Integrated-Circuit''', a bidirectional 2-wire bus for efficient inter-IC control.<br />
* http://www.esacademy.com/faq/i2c/index.htm<br />
<br />
=== IDSEL/AD ===<br />
Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?<br />
* http://www.techfest.com/hardware/bus/pci.htm<br />
* http://www.fpga4fun.com/PCI4.html<br />
<br />
=== IRQ ===<br />
Interrupt ReQuest (Handler).<br />
<br />
<br />
== J ==<br />
<br />
=== JTAG ===<br />
Debugging and test 4-wire interface named after an organization which defined it.<br />
<br />
== L ==<br />
<br />
=== LPC ===<br />
'''Low Pin Count''', an interface aimed at replacing the ISA bus.<br />
* http://www.intel.com/design/chipsets/industry/lpc.htm<br />
<br />
=== LRU ===<br />
'''Least Recently Used''', a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.<br />
* http://computer.laborlawtalk.com/Least%20Recently%20Used<br />
<br />
<br />
== M ==<br />
<br />
=== MII ===<br />
'''Media Independent Interface'''. This is a chip commonly found on ethernet devices, together with a PHY.<br />
* http://en.wikipedia.org/wiki/MII<br />
<br />
=== MMIO ===<br />
'''Memory-mapped I/O''' and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.<br />
* http://en.wikipedia.org/wiki/MMIO<br />
<br />
=== MPTable ===<br />
'''Multi Processor Table'''. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.<br />
* http://www.uruk.org/mps/<br />
* http://www.intel.com/design/pentium/datashts/242016.htm<br />
<br />
=== MTRR ===<br />
'''Memory Type Range Register'''. This can be used to control the way a processor accesses memory ranges.<br />
* http://en.wikipedia.org/wiki/MTRR<br />
<br />
<br />
== O ==<br />
<br />
=== OHCI ===<br />
'''Open Host Controller Interface'''. IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel).<br />
* http://en.wikipedia.org/wiki/Ohci<br />
* http://developer.intel.com/technology/1394/download/ohci_11.htm<br />
<br />
<br />
== P ==<br />
<br />
=== PAM ===<br />
'''Programmable Attribute Map'''. Hardware registers that describe how certain memory areas are accessed. The '''BIOS''' areas have a flash chip mapped on top of a piece of memory. By changing the '''PAM''' registers, accesses to these memory areas can be mapped to either the RAM or the flash device. '''Shadowing''' is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the '''PAM''' registers are part of the southbridge of a system.<br />
<br />
=== PAT ===<br />
'''Page Attribute Table'''. Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.<br />
* http://www.intel.com/design/pentium4/manuals/index_new.htm<br />
* http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10<br />
<br />
=== PAT ===<br />
Performance Acceleration Technology.<br />
* http://www.intel.com/design/chipsets/pat.htm<br />
<br />
=== PCI ===<br />
Peripheral Component Interconnect.<br />
* http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect<br />
<br />
=== PCI Configuration Space ===<br />
* http://en.wikipedia.org/wiki/PCI_Configuration_Space<br />
* http://www.techfest.com/hardware/bus/pci.htm<br />
<br />
=== PCI Express / PCIe ===<br />
* http://en.wikipedia.org/wiki/Pci_express<br />
<br />
=== PHY ===<br />
'''PHY layer device'''. A device that provides low level access to the physical layer.<br />
* http://en.wikipedia.org/wiki/PHY<br />
* http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer<br />
<br />
=== PIC ===<br />
A '''Programmable Interrupt Controller''' is a device to control peripheral devices, offloading the main CPU.<br />
* http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller<br />
* http://www.interq.or.jp/japan/se-inoue/e_pic1.htm<br />
<br />
=== PIO ===<br />
'''Programmed Input/Output''' interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.<br />
* http://en.wikipedia.org/wiki/Programmed_input/output<br />
<br />
=== PIR ===<br />
Programmable Interrupt Routing?<br />
<br />
=== PIRQ ===<br />
PCI IRQ routing table,<br />
* http://www.microsoft.com/whdc/archive/pciirq.mspx<br />
* http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm<br />
* Interesting tool?: https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view<br />
<br />
=== PLCC ===<br />
'''Plastic Leaded Chip Carrier''', a square surface-mount chip package.<br />
* http://www.webopedia.com/TERM/P/PLCC.html<br />
<br />
=== PLL ===<br />
'''Phase Locked Loop''' is a device to keep (electrical) signals synchronised throughout the system.<br />
* http://en.wikipedia.org/wiki/PLL<br />
<br />
=== POST ===<br />
The '''Power On Self Test''' is a test to check that devices the computer will rely on are functioning, and initializes devices.<br />
* http://en.wikipedia.org/wiki/Power-on_self_test<br />
<br />
== R ==<br />
<br />
=== RDMA ===<br />
'''Remote Direct Memory Access''' is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.<br />
* http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access<br />
<br />
=== RCS ===<br />
Revision control systems.<br />
<br />
== S ==<br />
<br />
=== SB ===<br />
'''Southbridge'''. Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...<br />
<br />
=== SBA ===<br />
SideBand Addressing.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
<br />
=== Shadow RAM ===<br />
RAM which content is copied from ROM residing at the same address for speedup purposes.<br />
<br />
=== SIO ===<br />
Serial Input/Output.<br />
* http://www.acronymfinder.com/af-query.asp?String=off&Acronym=sio&Find=Find&sourceid=mozilla-search<br />
<br />
=== SMBus ===<br />
The '''System Management Bus''' is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.<br />
* http://www.smbus.org/<br />
* http://www.computer-dictionary-online.org/index.asp?q=System%20Management%20Bus<br />
<br />
=== SMM ===<br />
'''System Management Mode'''. Processor mode that is mainly used for power management purposes.<br />
<br />
=== SMRAM ===<br />
System Management Random Access Memory.<br />
<br />
=== SPD ===<br />
'''Serial Presence Detect'''. On every (?) memory module there's an EPROM that provides the BIOS with information on how to properly configure the memory module.<br />
* http://www.simmtester.com/page/news/showpubnews.asp?num=101<br />
<br />
=== SPI ===<br />
The '''Serial Peripheral Interface Bus''' is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.<br />
* http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus<br />
<br />
=== SuperIO ===<br />
The '''SuperIO''' is the chip that provides floppy, serial and parallel functionality/ports.<br />
* http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html<br />
<br />
<br />
== T ==<br />
<br />
=== TLB ===<br />
'''Translation Lookaside Buffer'''. The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.<br />
* http://www.linuxelectrons.com/article.php/20031021142247752<br />
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1<br />
<br />
<br />
== U ==<br />
<br />
=== UC ===<br />
Strong '''UnCacheable'''. Memory type setting in MTRR/PAT.<br />
<br />
=== UC ===<br />
'''UnCacheable'''. Memory type setting in MTRR/PAT.<br />
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3<br />
<br />
=== UHCI ===<br />
'''Universal Host Controller Interface'''. USB standard.<br />
* http://en.wikipedia.org/wiki/UHCI<br />
* http://developer.intel.com/technology/usb/uhci11d.htm<br />
<br />
<br />
== V ==<br />
<br />
=== VGAcon ===<br />
The purpose of the '''VGAcon''' (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students FPGA project).<br />
* http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm<br />
<br />
=== VID ===<br />
'''Vendor ID''', a way of identifying the hardware manufacturer.<br />
* http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx<br />
* http://pciids.sourceforge.net/<br />
A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.<br />
<br />
=== VMEBus ===<br />
'''VERSAmodule Eurocard Bus''' or '''Versa Module Europa Bus'''. A computer bus originally developed for the Motorola 68000.<br />
* http://en.wikipedia.org/wiki/VMEbus<br />
<br />
== W ==<br />
<br />
=== WB ===<br />
Write-Back. Memory type setting in MTRR/PAT.<br />
<br />
=== WC ===<br />
Write-Combining. Memory type setting in MTRR/PAT.<br />
<br />
=== WP ===<br />
Write Protected. Memory type setting in MTRR/PAT.<br />
<br />
=== WT ===<br />
Write-Through. Memory type setting in MTRR/PAT.<br />
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3</div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=4796Board:asus/a8n e2007-08-12T02:51:02Z<p>Quux: /* Before you begin */ no hypervisor in flash on s 939 :-(</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=4795Board:asus/a8n e2007-08-12T01:43:56Z<p>Quux: /* Before you begin */</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=4794Board:asus/a8n e2007-08-12T01:43:40Z<p>Quux: /* Before you begin */</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=4787Board:asus/a8n e2007-08-12T01:30:30Z<p>Quux: /* known issues */</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=4786Board:asus/a8n e2007-08-12T01:30:14Z<p>Quux: /* Before you begin */</p>
<hr />
<div></div>Quuxhttps://www.coreboot.org/index.php?title=Board:asus/a8n_e&diff=4784Board:asus/a8n e2007-08-12T01:18:57Z<p>Quux: /* Before you begin */</p>
<hr />
<div></div>Quux