Difference between revisions of "ACPI"

From coreboot
Jump to navigation Jump to search
m (grammar)
Line 3: Line 3:
= ACPI setup HOWTO =
= ACPI setup HOWTO =


Please have a look to files in the [http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/mainboard/asus/a8v-e_se src/mainboard/asus/a8v-e_se]. Please also checkout http://acpi.info, which contains the ACPI specification.
Please have a look at the files in [http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/mainboard/asus/a8v-e_se src/mainboard/asus/a8v-e_se]. Please also check out http://acpi.info, which contains the ACPI specification.


== Setup hardware ==
== Set up hardware ==


Setup the '''PMIO base address''' to some known address, and setup the desired ACPI IRQ (usually IRQ9). Sometimes it is called SCI interrupt.
Set the '''PMIO base address''' to some known address, and set up the desired ACPI IRQ (usually IRQ9). Sometimes it is called SCI interrupt.


== Fill FADT ==
== Fill FADT ==
Line 27: Line 27:
</pre>
</pre>


In this example the ACPI IRQ is 9, and the '''PM1A event block''' starts at VT8237R_ACPI_IO_BASE. You may obtain some values from '''cat /proc/ioport''' if running with proprietary BIOS. Not all blocks are necessary usually only PM1A PMTMR and GPE0 are used. Please note that this table has the I/O port information stored twice using different formats. Please consult the ACPI specification for details, mostly could be used what are the defaults in the '''fadt.c'''.
In this example the ACPI IRQ is 9, and the '''PM1A event block''' starts at VT8237R_ACPI_IO_BASE. You may obtain some values from '''cat /proc/ioport''' if running with the proprietary BIOS. Not all blocks are necessary&mdash;usually only PM1A PMTMR and GPE0 are used. Please note that this table has the I/O port information stored twice using different formats. Please consult the ACPI specification for details. Most settings in '''fadt.c''' can use their default values.


== Fill DSDT ==
== Fill DSDT ==
Line 57: Line 57:
</pre>
</pre>


This defines the SLP_TYP fields in PM1A register. In my case I need to store 010 to perform soft off, and 000 to wakeup. Modify it to fit your chipset needs.
This defines the SLP_TYP fields in PM1A register. In my case I need to store 010 to perform soft-off, and 000 to wake up. Modify it to fit your chipset needs.


==== Interrupt routing in DSDT ====
==== Interrupt routing in DSDT ====

Revision as of 23:33, 16 July 2009