Difference between revisions of "ACPI"
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(New chapter about S3) |
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=== Suspend to RAM === | === Suspend to RAM === | ||
There are patches on ML which add support for suspend to RAM in coreboot. Checklist of things which needs to be setup correctly: | There are patches on ML which add support for suspend to RAM in coreboot. The resume start of the computer does not differ until OS waking vector is executed instead of payload. | ||
Checklist of things which needs to be setup correctly: | |||
* Supend clocks, SUSA/B/C plane pins | * Supend clocks, SUSA/B/C plane pins | ||
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* Chipset tweaks for S3 (like various signal delays) | * Chipset tweaks for S3 (like various signal delays) | ||
* CPU tweaks (for AMD the PM1 and PM2 registers and SMAF codes) | * CPU tweaks (for AMD the PM1 and PM2 registers and SMAF codes) | ||
* _RAMBASE of coreboot setup to 31MB and set LB_MEM_TOPK to 32MB | |||
* make sure new code does not corrupt any memory | |||
* make sure that you reserve _RAMBASE - LB_MEM_TOPK | |||
* SMP might need some fixes | |||
=== Debugging ACPI === | === Debugging ACPI === | ||