The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
The AMD IMC register interface visible from PCI space is documented in the AMD reference guides. This page tries to cover everything else which is not documented elsewhere.
The embedded controller is an 8051 CPU most likely derived from SMSC LPC47N350 Data Sheet or any recent SMSC embedded controller core. As the 8051, it has 3 memory spaces. The SFR, internal RAM and external space where the hardware has specific registers mapped. The code is fetched from 16KB? region of flash the base address is set to 0xFFF20000 (in SB710).
The EC is turned on if the soft straps are set to on during the init of the southbridge, this is documented in the SB datasheet. To make it operational you will need to modify the strap bits and include the IMC firmware in the coreboot image. The 8051 reset vector is first instruction. The firmware itself contains a magic _AMD_IMC_C and you can check validateImcFirmware() how it works.
To check if IMC is active check if PCI 0:14.3 0x40 bit7 set.