The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
This HOWTO explains how to use coreboot on the ASUS A8N-E board.
|CPU works||OK||Tested: AMD Athlon(tm) 64 Processor 3000+ and 3200+.|
|L1 cache enabled||OK||CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)|
|L2 cache enabled||OK||CPU: L2 Cache: 512K (64 bytes/line)|
|L3 cache enabled||N/A|
|Multiple CPU support||N/A|
|DDR||OK||Tested with one DIMM in slot DIMM_B1 (see manual). Since r3614 it's also possible to use a single DIMM in slot DIMM_B2.|
|Dual channel support||Untested|
|On-board IDE 3.5"||OK||Tested: Primary IDE (master and slave) and secondary IDE (master and slave).|
|On-board IDE 2.5"||N/A|
|On-board USB||OK||Tested: USB keyboard (on each of the 10 possible USB ports).|
|On-board Smartcard reader||N/A|
|On-board SD card reader||N/A|
|ISA add-on cards||N/A|
|Audio/Modem-Riser (AMR/CNR) cards||N/A|
|PCI add-on cards||OK||Tested: PCI VGA card in all three PCI slots.|
|Mini-PCI add-on cards||N/A|
|Mini-PCI-Express add-on cards||Unknown|
|PCI-X add-on cards||N/A|
|AGP graphics cards||N/A|
|PCI Express x1 add-on cards||OK||Both PCIe x1 slots works fine (tested with a network card).|
|PCI Express x2 add-on cards||N/A|
|PCI Express x4 add-on cards||Untested|
|PCI Express x8 add-on cards||N/A|
|PCI Express x16 add-on cards||WIP||Doesn't seem to work, yet (?)|
|PCI Express x32 add-on cards||N/A|
|HTX add-on cards||N/A|
|Legacy / Super I/O|
|Serial port 1 (COM1)||OK|
|Serial port 2 (COM2)||N/A|
|Parallel port||OK||Tested with a printer|
|Sensors / fan control||OK||Tested: sensors reports K8 core temp. (kernel module k8temp) and various other values from the IT8712F Super I/O (kernel module it87).|
|CPU frequency scaling||No||Needs (at least partial) ACPI support.|
|Other powersaving features||N/A|
|ACPI||No||There's no ACPI implementation for this board.|
|Nonstandard LEDs||OK||There's a green LED on the board which is enabled when the board is powered-on. Works out of the box, no special coreboot support required.|
|High precision event timers (HPET)||OK||The hardware supports it, but you currently need the hpet=force Linux kernel parameter. Reduces the number of wakeups in powertop drastically.|
|Random number generator (RNG)||N/A|
|Wake on modem ring||Untested|
|Wake on LAN||N/A||The on-board ethernet device doesn't seem to support WOL (also not mentioned in the manual).|
|Wake on keyboard||Untested|
|Wake on mouse||Untested|
|Flashrom||OK||Works fine when booted with BIOS and also with coreboot.|
See the Build HOWTO for information on how to build coreboot for this board.
- The MAC address is stored in flash for almost all CK804/MCP55 boards. All of these boards flashed with coreboot probably have the same MAC address. See src/southbridge/nvidia/ck804/romstrap.inc and src/southbridge/nvidia/mcp55/romstrap.inc for details. On some of these boards, the MAC address is stored in a separate EEPROM, but you can't count on that.
If you can help out with this, please join the mailing list and let us know!
|This work is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or any later version. This work is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.|